Hassan Aboushady

Orcid: 0000-0003-3489-5968

According to our database1, Hassan Aboushady authored at least 60 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
An End-To-End Neuromorphic Radio Classification System With an Efficient Sigma-Delta-Based Spike Encoding Scheme.
IEEE Trans. Artif. Intell., April, 2024

A 10.8GS/s, 84MHz-BW RF Bandpass ΣΔ ADC with a 89dB-SFDR and a 62dB-SNDR for LTE/5G Receivers.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Covert Communication Channels Based On Hardware Trojans: Open-Source Dataset and AI-Based Detection.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty: The KDT Resilient Trust Project.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

2023
Anti-Piracy Design of RF Transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

Leaking Wireless ICs via Hardware Trojan-Infected Synchronization.
IEEE Trans. Dependable Secur. Comput., 2023

2022
RF Transceiver Security Against Piracy Attacks.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Digital-to-Analog Hardware Trojan Attacks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Digitally Assisted Mixed-Signal Circuit Security.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Tunable Filtenna With DGS Loaded Resonators for a Cognitive Radio System Based on an SDR Transceiver.
IEEE Access, 2022

Systematic Design For Multistage Feed-forward Op-amp For High-Speed Continuous-Time ∑Δ ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Common mode control loop for current mode logic-based circuits in FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

RF to Bits Highly Tunable Sub-1 pJ/bit Digital Beamforming Receiver Architectures for 5G Applications.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

SyncLock: RF Transceiver Security Using Synchronization Locking.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Anti-Piracy of Analog and Mixed-Signal Circuits in FD-SOI.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Analog and Mixed-Signal IC Security via Sizing Camouflaging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A 6.4 GHz Continuous-Time ΣΔ ADC Using Body-Biased Feedforward Op-Amps in 28nm-FDSOI.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Deep Learning Modulation Recognition for RF Spectrum Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Cognitive Radio Circuits and Systems - Application to Digitizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A 1.5-to-3.0GHz Tunable RF Sigma-Delta ADC With a Fixed Set of Coefficients and a Programmable Loop Delay.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A g<sub>m</sub>/I<sub>D</sub> Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Securing Programmable Analog ICs Against Piracy.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application.
Proceedings of the 16th International Conference on Synthesis, 2019

Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

MixLock: Securing Mixed-Signal Circuits via Logic Locking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2017
4th order capacitively-coupled LC-based ΣΔ modulator.
Microelectron. J., 2017

High-Speed Plastic Integrated Circuits: Process Integration, Design, and Test.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

2016
Delta-sigma modulator based spectrum sensing transceiver.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Phase Noise Effect on Sine-Shaped Feedback DACs Used in Continuous-Time ΣΔ ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014
An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Design of RF BAW-based ΣΔ Modulators.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Low-power comb decimation filter for RF Sigma-Delta ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A 4th Order 3.6 GS/s RF ΣΔ ADC With a FoM of 1 pJ/bit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
Holistic modeling of embedded systems with multi-discipline feedback: Application to a Precollision Mitigation Braking System.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Sine-shaping mixer for continuous-time ΣΔ ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 4<sup>th</sup> order subsampled RF ∑Δ ADC centered at 2.4GHz with a sine-shaped feedback DAC.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΔΣ ADC with a FoM of 1pJ/bit in 130nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Systematic design of continuous-time ΣΔ modulator with VCO-based quantizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Jitter analysis of bandpass continuous-time ΣΔMs for different feedback DAC shapes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A generalized approach to design CT ΣΔMs based on FIR DAC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Modeling jitter in Continuous-Time sigma-delta modulators.
Proceedings of the 2010 IEEE International Behavioral Modeling and Simulation Conference, 2010

SystemC-AMS Models for Low-Power Heterogeneous Designs: Application to a WSN for the Detection of Seismic Perturbations.
Proceedings of the ARCS '10, 2010

2009
Automatic Model Refinement of GmC Integrators for High-level Simulation of Continuous-time Sigma-Delta Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Effect of OP-amp Phase Margin on SC SigmaDelta Modulator with Bulk Acoustic Wave Resonators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Q-enhanced LC bandpass filter using CAIRO+.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSN.
Proceedings of the Design, Automation and Test in Europe, 2008

2006
Undersampled LC bandpass Sigma Delta modulators with feedback FIRDACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Systematic design method for LC bandpass Sigma Delta modulators with feedback FIRDACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Scaling Input Signal Swings of Overloaded Integrators in Resonator-based Sigma-Delta Modulators.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Design of continuous-time ΣΔ modulators with sine-shaped feedback DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Loop delay compensation in bandpass continuous-time Sigma Delta modulators without additional feedback coefficients.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators.
Proceedings of the 2004 Design, 2004

2002
Résumés de thèse.
Ann. des Télécommunications, 2002

Systematic approach for discrete-time to continuous-time transformation of Sigma-Delta modulators.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Low-power design of low-voltage current-mode integrators for continuous-time Sigma-Delta modulators.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Systematic design of high-linearity current-mode integrators for low-power continuous-time ΣΔ modulators.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1999
A current-mode continuous-time Sigma-Delta modulator with delayed return-to-zero feedback.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A third-order current-mode continuous-time ΣΔ modulator.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Jitter effects in continuous-time ΣΔ modulators with delayed return-to-zero feedback.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


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