Hassan A. Salamy

According to our database, Hassan A. Salamy authored at least 31 papers between 2006 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis.

Dulana Rupanetti, Hassan A. Salamy, Cheol-Hong Min, Kundan Nepal

Int. J. Parallel Emergent Distributed Syst., 2022

2021

Thermal and energy-aware utilisation management on MPSoC architectures.

Dulana Rupanetti, Hassan A. Salamy

Int. J. Parallel Emergent Distributed Syst., 2021

Energy-Aware Task Migration Through Ant-Colony Optimization for Multiprocessors.

Dulana Rupanetti, Hassan A. Salamy

Proceedings of the 12th IEEE Annual Ubiquitous Computing, 2021

Data Balanced Bagging Ensemble of Convolutional- LSTM Neural Networks for Time Series Data Classification with an Imbalanced Dataset.

Matthew Ward, Kevin Malmsten, Hassan A. Salamy, Cheol-Hong Min

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Energy-Aware Schedules Under Chip Reliability Constraint for Multi-Processor Systems-on-a-Chip.

Hassan A. Salamy

J. Circuits Syst. Comput., 2020

Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications.

Dulana Rupanetti, Kundan Nepal, Hassan A. Salamy, Cheol-Hong Min

Proceedings of the 10th Annual Computing and Communication Workshop and Conference, 2020

2019

Task allocation, migration and scheduling for energy-efficient real-time multiprocessor architectures.

Dulana Rupanetti, Hassan A. Salamy

J. Syst. Archit., 2019

An Effective Technique to Higher Throughput for Streaming Applications on an MPSoC.

Hassan A. Salamy

J. Comput., 2019

Thermal-Constrained. Energy-Aware Load Management on MPSoC Architectures.

Dulana Rupanetti, Hassan A. Salamy

Proceedings of the 10th IEEE Annual Ubiquitous Computing, 2019

Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition.

Matthew Ward, Cheol-Hong Min, Hassan A. Salamy, Kundan Nepal

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Energy Efficient Scheduling with Task Migration on MPSoC Architectures.

Dulana Rupanetti, Hassan A. Salamy

Proceedings of the 2019 IEEE International Conference on Electro Information Technology, 2019

2017

Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC.

Hassan A. Salamy, Semih Aslan

J. Circuits Syst. Comput., 2017

An effective approach to schedule time reduction on multi-core embedded systems.

Hassan A. Salamy

Comput. Electr. Eng., 2017

2016

Energy efficient scheduling for a stream of applications on an MPSoC under throughput constraints.

Hassan A. Salamy, Mugdha Tasgaonkar

Proceedings of the 2016 IEEE International Conference on Electro Information Technology, 2016

2013

Energy-aware schedule optimization on multicore systems.

Hassan A. Salamy, Semih Aslan

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A high-level synthesis and verification tool for application specific k^th Root Processing Engine.

Semih Aslan, Hassan A. Salamy, Jafar Saniie

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Task scheduling on multicores under energy and power constraints.

Hassan A. Salamy, Semih Aslan, Divya Methukumalli

Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

2012

An ILP solution to address code generation for embedded applications on digital signal processors.

Hassan A. Salamy, J. Ramanujam

ACM Trans. Design Autom. Electr. Syst., 2012

Storage Optimization through Offset Assignment with Variable Coalescing.

Hassan A. Salamy, J. Ramanujam

ACM Trans. Embed. Comput. Syst., 2012

An Effective Solution to Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip.

Hassan A. Salamy, J. Ramanujam

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Code Size Reduction for Array Intensive Applications on Digital Signal Processors.

Hassan A. Salamy, J. Ramanujam

J. Circuits Syst. Comput., 2012

Minimizing address arithmetic instructions in embedded applications on DSPs.

Hassan A. Salamy

Comput. Electr. Eng., 2012

An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates.

Hassan A. Salamy, Haidar Harmanani

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011

Compact code generation for embedded applications on digital signal processors.

Hassan A. Salamy

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

An optimal formulation for test scheduling network-on-chip using multiple clock rates.

Hassan A. Salamy, Haidar M. Harmanani

Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2009

A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip.

Hassan A. Salamy, J. Ramanujam

Proceedings of the High Performance Embedded Architectures and Compilers, 2009

2008

Storage optimization through code size reduction for digital signal processors.

Hassan A. Salamy, J. Ramanujam

Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

Optimal address register allocation for arrays in DSP applications.

Hassan A. Salamy, J. Ramanujam

Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

2006

Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic Algorithm.

Haidar M. Harmanani, Hassan A. Salamy

J. Circuits Syst. Comput., 2006

A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints.

Haidar M. Harmanani, Hassan A. Salamy

Int. J. Comput. Intell. Appl., 2006

An Effective Heuristic for Simple Offset Assignment with Variable Coalescing.

Hassan A. Salamy, J. Ramanujam

Proceedings of the Languages and Compilers for Parallel Computing, 2006