Hasita Veluri
Orcid: 0000-0002-0549-8341
According to our database1,
Hasita Veluri
authored at least 7 papers
between 2019 and 2025.
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Bibliography
2025
A Low-Latency DNN Accelerator Enabled by DFT-Based Convolution Execution Within Crossbar Arrays.
IEEE Trans. Neural Networks Learn. Syst., January, 2025
2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
2023
IEEE Trans. Neural Networks Learn. Syst., August, 2023
2022
Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm<sup>2</sup>/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks.
IEEE Internet Things J., 2021
2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Design of Artificial Spiking Neuron with SiO2 Memristive Synapse to Demonstrate Neuron-Level Spike Timing Dependent Plasticity.
Proceedings of the International Conference on IC Design and Technology, 2019