Hasan Erdem Yantir

Orcid: 0000-0002-0096-0365

According to our database1, Hasan Erdem Yantir authored at least 21 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Architectural Trade-Off Analysis for Accelerating LSTM Network Using Radix-r OBC Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

An Open-Source eFPGA-based SoC Design for Computation Acceleration.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
Toward the Optimal Design and FPGA Implementation of Spiking Neural Networks.
IEEE Trans. Neural Networks Learn. Syst., 2022

In-Memory Associative Processors: Tutorial, Potential, and Challenges.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A hardware/software co-design methodology for in-memory processors.
J. Parallel Distributed Comput., 2022

Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs.
IEEE Embed. Syst. Lett., 2022

2021
IMCA: An Efficient In-Memory Convolution Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2020
An Efficient 2D Discrete Cosine Transform Processor for Multimedia Applications.
Proceedings of the 28th Signal Processing and Communications Applications Conference, 2020

2019
Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Efficient Acceleration of Computation Using Associative In-memory Processing.
PhD thesis, 2018

A Two-Dimensional Associative Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Power optimization techniques for associative processors.
J. Syst. Archit., 2018

A Hybrid Approximate Computing Approach for Associative In-Memory Processors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Low-Power Resistive Associative Processor Implementation Through the Multi-Compare.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Rapid in-memory matrix multiplication using associative processor.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Approximate Memristive In-memory Computing.
ACM Trans. Embed. Comput. Syst., 2017

Efficient pulsed-latch implementation for multiport register files: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

2016
Process variations-aware resistive associative processor design.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2014
An Efficient Heterogeneous Register File Implementation for FPGAs.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Application specific multi-port memory customization in FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013


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