Haruyoshi Yonekawa

According to our database, Haruyoshi Yonekawa authored at least 10 papers between 2016 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers.

Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato

IEICE Trans. Inf. Syst., 2019

2018

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

IEEE J. Solid State Circuits, 2018

A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor.

Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA.

Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

In-memory area-efficient signal streaming processor design for binary neural networks.

Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA.

Haruyoshi Yonekawa, Hiroki Nakahara

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA.

Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato

Proceedings of the International Conference on Field Programmable Technology, 2017

A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA.

Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only).

Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

A memory-based realization of a binarized deep convolutional neural network.

Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016