Haruhiko Ichino

According to our database, Haruhiko Ichino authored at least 14 papers between 1989 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

MAC protocol based on cross-layer design methodology for fast link in wireless communication systems.

Shoko Ohteru, Keiji Kishine, Haruhiko Ichino

IEICE Electron. Express, 2007

2005

Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks.

Kazuhiko Terada, Kenji Kawai, Osamu Ishida, Keiji Kishine, Noboru Iwasaki, Haruhiko Ichino

IEICE Trans. Commun., 2005

2004

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits.

Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino

IEEE J. Solid State Circuits, 2004

2002

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX.

Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino

IEEE J. Solid State Circuits, 2002

2000

A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI.

Kenji Kawai, Haruhiko Ichino

IEEE J. Solid State Circuits, 2000

A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit.

Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs.

Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino

IEEE J. Solid State Circuits, 1999

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design.

Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino

IEEE J. Solid State Circuits, 1999

1998

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing.

Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino

IEEE J. Solid State Circuits, 1998

1997

A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic.

Keiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino

IEEE J. Solid State Circuits, 1997

1995

Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops.

Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi

IEEE J. Solid State Circuits, January, 1995

1994

Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit.

Kiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi

IEEE J. Solid State Circuits, July, 1994

High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology.

Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi

IEEE J. Solid State Circuits, May, 1994

1989

18-GHz 1/8 dynamic frequency divider using Si bipolar technologies.

Haruhiko Ichino, Noboru Ishihara, Masao Suzuki, Shinsuke Konaka

IEEE J. Solid State Circuits, December, 1989