Haruhiko Abe
According to our database1,
Haruhiko Abe
authored at least 2 papers
in 1996.
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Bibliography
1996
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.
IEEE J. Solid State Circuits, 1996
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996