Harufusa Kondoh

According to our database1, Harufusa Kondoh authored at least 8 papers between 1991 and 2002.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2002
A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000
14-bit 2.2-MS/s sigma-delta ADC's.
IEEE J. Solid State Circuits, 2000

SNDR sensitivity analysis for cascaded ΣΔ modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1996
A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication.
IEEE J. Solid State Circuits, 1996

1993
A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture.
IEEE J. Solid State Circuits, July, 1993

1991
A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture.
IEEE J. Solid State Circuits, November, 1991

A 10-b 70-MS/s CMOS D/A converter.
IEEE J. Solid State Circuits, April, 1991

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses.
IEEE J. Solid State Circuits, April, 1991


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