Harshita Vallabhaneni

According to our database¹, Harshita Vallabhaneni authored at least 2 papers between 2016 and 2017.

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2017

Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016

Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2016