Harshad Dhotre

According to our database, Harshad Dhotre authored at least 7 papers between 2016 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Pattern analysis for power safe testing and prediction using machine learning.

Harshad Dhotre

PhD thesis, 2019

Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements.

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler

Proceedings of the IEEE Latin American Test Symposium, 2019

Machine Learning-based Prediction of Test Power.

Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing.

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017

Machine learning based test pattern analysis for localizing critical power activity areas.

Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Identification of Efficient Clustering Techniques for Test Power Activity on the Layout.

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Automated Optimization of Scan Chain Structure for Test Compression-Based Designs.

Harshad Dhotre, Mehdi Dehbashi, Ulrike Pfannkuchen, Klaus Hofmann

Proceedings of the 25th IEEE Asian Test Symposium, 2016