Harry Sidiropoulos

George Chatzikonstantis

Georgios Chatzikonstantis

Christos Strydis

Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018

2017

From Knights Corner to Landing: A Case Study Based on a Hodgkin-Huxley Neuron Simulator.

[BibT_eX]

[DOI]

George Chatzikonstantis

Proceedings of the High Performance Computing, 2017

Algorithmic and memory optimizations on multiple application mapping onto FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

2016

BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations.

[BibT_eX]

[DOI]

Georgios Smaragdos

CoRR, 2016

2015

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools.

[BibT_eX]

[DOI]

Dionysios Diamantopoulos

Konstantinos Maragos

Shalina Percy Delicia

Jürgen Becker

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

A novel 3-D FPGA architecture targeting communication intensive applications.

[BibT_eX]

[DOI]

J. Syst. Archit., 2014

A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

2013

JITPR: A framework for supporting fast application's implementation onto FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2013

On supporting rapid exploration of memory hierarchies onto FPGAs.

[BibT_eX]

[DOI]

Christoforos E. Economakos

J. Syst. Archit., 2013

Rapid prototyping of digital controllers using FPGAs and ESL/HLS design methodologies.

[BibT_eX]

[DOI]

George Economakos

Proceedings of the 2013 19th International Conference on Automation and Computing, 2013

A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Efficient C level hardware design for floating point biomedical DSP applications.

[BibT_eX]

[DOI]

Christoforos E. Economakos

Efthymia Kazakou

George Economakos

Proceedings of the 13th IEEE International Conference on BioInformatics and BioEngineering, 2013

2012

On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011

A Framework for Architecture-Level Exploration of 3-D FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010

NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGAS.

[BibT_eX]

[DOI]