Harris E. Michail
According to our database1,
Harris E. Michail
authored at least 44 papers
between 2004 and 2022.
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Bibliography
2022
Machine Learning Analysis of Pedestrians' Hazard Anticipation from Eye Tracking Data.
Proceedings of the Twelfth International Workshop on Agents in Traffic and Transportation co-located with the the 31st International Joint Conference on Artificial Intelligence and the 25th European Conference on Artificial Intelligence (IJCAI-ECAI 2022), 2022
2018
Proceedings of the 50th Computer Simulation Conference, 2018
2016
Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures.
Microprocess. Microsystems, 2016
J. Circuits Syst. Comput., 2016
2015
Proceedings of the Conference on Summer Computer Simulation, 2015
Proceedings of the 4th Mediterranean Conference on Embedded Computing, 2015
Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, 2015
Proceedings of the IEEE EUROCON 2015, 2015
2014
On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs.
Integr., 2014
IET Comput. Digit. Tech., 2014
Distribution of Cultural Content through Exploitation of Cryptographic Algorithms and Hardware Identification.
Proceedings of the Digital Heritage. Progress in Cultural Heritaage: Documentation, Preservation, and Protection, 2014
2013
A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families.
J. Circuits Syst. Comput., 2013
IET Comput. Digit. Tech., 2013
2012
ACM Trans. Reconfigurable Technol. Syst., 2012
J. Supercomput., 2012
On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function.
Proceedings of the SECRYPT 2012, 2012
High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach.
Proceedings of the SECRYPT 2012, 2012
An Intelligent Transportation System for Accident Risk Index Quantification.
Proceedings of the ICEIS 2012 - Proceedings of the 14th International Conference on Enterprise Information Systems, Volume 1, Wroclaw, Poland, 28 June, 2012
Proceedings of the Progress in Cultural Heritage Preservation, 2012
Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation, 2012
2011
A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization.
IEEE Trans. Signal Process., 2011
J. Circuits Syst. Comput., 2011
2010
Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy.
J. Signal Process. Syst., 2010
Ultra High Speed SHA-256 Hashing Cryptographic Module for IPSec Hardware/Software Codesign.
Proceedings of the SECRYPT 2010, 2010
Proceedings of the Aging Friendly Technology for Health and Independence, 2010
Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
IEEE Trans. Dependable Secur. Comput., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Integr., 2009
Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse.
IET Comput. Digit. Tech., 2009
2008
J. Comput. Networks Commun., 2008
2007
Int. J. Secur. Networks, 2007
Proceedings of the 15th International Conference on Digital Signal Processing, 2007
Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007
Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications.
J. Supercomput., 2006
Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers.
J. Low Power Electron., 2006
Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
VLSI design and implementation of reconfigurable cryptographic systems for symmetric encryption.
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Novel high throughput implementation of SHA-256 hash function through pre-computation technique.
Proceedings of the 12th IEEE International Conference on Electronics, 2005
2004
Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004