Haroon Waris

Orcid: 0000-0003-4670-3919

According to our database1, Haroon Waris authored at least 14 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024

2023
Exact and Approximate Squarers for Error-Tolerant Applications.
IEEE Trans. Computers, July, 2023

Approximate Softmax Functions for Energy-Efficient Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2023

2022
AxRMs: Approximate Recursive Multipliers Using High-Performance Building Blocks.
IEEE Trans. Emerg. Top. Comput., 2022

Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers.
IEEE Trans. Emerg. Top. Comput., 2022

Architectural-Space Exploration of Energy-Efficient Approximate Arithmetic Units for Error-Tolerant Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

An Automated Logic-Level Framework for Approximate Modular Arithmetic Circuits.
Proceedings of the Approximate Computing, 2022

2021
AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication.
J. Signal Process. Syst., 2021

Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning.
IEEE Trans. Sustain. Comput., 2021

AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
Hybrid Low Radix Encoding-Based Approximate Booth Multipliers.
IEEE Trans. Circuits Syst., 2020

2019
High-performance approximate half and full adder cells using NAND logic gate.
IEICE Electron. Express, 2019

Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

2018
Design Exploration of Small Bit-Width Multipliers Using Approximate Logic Design (ALD) Tool.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018


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