Haris Lekatsas

According to our database1, Haris Lekatsas authored at least 36 papers between 1998 and 2010.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2010
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2010

High-performance operating system controlled online memory compression.
ACM Trans. Embed. Comput. Syst., 2010

Online memory compression for embedded systems.
ACM Trans. Embed. Comput. Syst., 2010

2008
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm.
Proceedings of the 2008 Data Compression Conference (DCC 2008), 2008

Adaptive Filesystem Compression for Embedded Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Code Decompression Unit Design for VLIW Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2006
Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

High-performance operating system controlled memory compression.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Approximate arithmetic coding for bus transition reduction in low power designs.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

CRAMES: compressed RAM for embedded systems.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Guest editorial: Special issue on embedded systems and security.
ACM Trans. Embed. Comput. Syst., 2004

Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems.
IEEE Des. Test Comput., 2004

2003
A dictionary-based en/decoding scheme for low-power data buses.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding.
Proceedings of the 2003 Data Compression Conference (DCC 2003), 2003

Profile-Driven Selective Code Compression.
Proceedings of the 2003 Design, 2003

Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses.
Proceedings of the 2003 Design, 2003

CoCo: a hardware/software platform for rapid prototyping of code compression technologies.
Proceedings of the 40th Design Automation Conference, 2003

Multi-parametric improvements for embedded systems using code-placement and address bus coding.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Code Compression for VLIW Processors Using Variable-to-Fixed Coding.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

An Adaptive Dictionary Encoding Scheme for SOC Data Buses.
Proceedings of the 2002 Design, 2002

Design of an one-cycle decompression hardware for performance increase in embedded systems.
Proceedings of the 39th Design Automation Conference, 2002

1-cycle code decompression circuitry for performance increase of Xtensa-1040-based embedded systems.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
A code decompression architecture for VLIW processors.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Design and simulation of a pipelined decompression architecture for embedded systems.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Code Compression for VLIW Processors.
Proceedings of the Data Compression Conference, 2001

A<sup>2</sup>BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs.
Proceedings of the 38th Design Automation Conference, 2001

2000
A Decompression Architecture for Low Power Embedded Systems.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Arithmetic Coding for Low Power Embedded System Design.
Proceedings of the Data Compression Conference, 2000

Code compression for low power embedded system design.
Proceedings of the 37th Conference on Design Automation, 2000

Code compression as a variable in hardware/software co-design.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
SAMC: a code compression algorithm for embedded processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Random Access Decompression Using Binary Arithmetic Coding.
Proceedings of the Data Compression Conference, 1999

1998
Code Compression for Embedded Systems.
Proceedings of the 35th Conference on Design Automation, 1998


  Loading...