Haris Javaid

Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022

Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE International Conference on Distributed Computing Systems, 2022

Efficient FPGA-based ECDSA Verification Engine for Permissioned Blockchains.

[BibT_eX]

[DOI]

Rashmi Agrawal

Ji Yang

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2020

Hardware Trojan Mitigation in Pipelined MPSoCs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2020

A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

REALM: Reduced-Error Approximate Log-based Integer Multiplier.

[BibT_eX]

[DOI]

Hassaan Saadat

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

WEID: Worst-case Error Improvement in Approximate Dividers.

[BibT_eX]

[DOI]

Hassaan Saadat

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Optimizing Validation Phase of Hyperledger Fabric.

[BibT_eX]

[DOI]

Chengchen Hu

Gordon J. Brebner

Proceedings of the 27th IEEE International Symposium on Modeling, 2019

Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias.

[BibT_eX]

[DOI]

Hassaan Saadat

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FastProxy: Hardware and Software Acceleration of Stratum Mining Proxy.

[BibT_eX]

[DOI]

Proceedings of the Crypto Valley Conference on Blockchain Technology, 2019

2016

Switchable cache: utilising dark silicon for application specific cache optimisations.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2016

2015

Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs.

[BibT_eX]

[DOI]

Isuru Nawinne

Swarnalatha Radhakrishnan

Roshan G. Ragel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

E-pipeline: elastic hardware/software pipelines on a many-core fabric.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Malleable NoC: dark silicon inspired adaptable Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

SuperNet: multimode interconnect architecture for manycore chips.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

ADAPT: An adaptive manycore methodology for software pipelined applications.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs).

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Hardware-based fast exploration of cache hierarchies in application specific MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs.

[BibT_eX]

[DOI]

Hong Chinh Doan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Pipelined Multiprocessor System-on-Chip for Multimedia.

[BibT_eX]

[DOI]

Springer, ISBN: 978-3-319-01112-7, 2014

2013

A case study on exploration of last-level cache for energy reduction in DDR3 DRAM.

[BibT_eX]

[DOI]

Su Myat Min

Thannirmalai Somu Muthukaruppan

Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

Energy-aware synthesis of application specific MPSoCs.

[BibT_eX]

[DOI]

Tulika Mitra

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

System-level optimization of on-chip communication using express links for throughput constrained MPSoCs.

[BibT_eX]

[DOI]

Haseeb Bokhari

Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs.

[BibT_eX]

[DOI]

Su Myat Min

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

RExCache: Rapid exploration of unified last-level cache.

[BibT_eX]

[DOI]

Su Myat Min

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Multi-mode pipelined MPSoCs for streaming applications.

[BibT_eX]

[DOI]

Daniel Witono

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Analyses and Optimisations for Pipelined MPSoCs.

[BibT_eX]

[DOI]

PhD thesis, 2012

2011

System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos.

[BibT_eX]

[DOI]

Hong Chinh Doan

Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Fidelity metrics for estimation models.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Rapid runtime estimation methods for pipelined MPSoCs.

[BibT_eX]

[DOI]

Andhi Janapsatya

Mohammad Shihabul Haque

Proceedings of the Design, Automation and Test in Europe, 2010

Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications.

[BibT_eX]

[DOI]

Xin He

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009

A design flow for application specific heterogeneous pipelined multiprocessor systems.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study.

[BibT_eX]

[DOI]