Hariprasath Venkatram

According to our database1, Hariprasath Venkatram authored at least 16 papers between 2010 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2015
A Continuous-Time ΔΣ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information.
IEEE J. Solid State Circuits, 2014

Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling.
IEEE J. Solid State Circuits, 2014

A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
Detection and Correction Methods for Single Event Effects in Analog to Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 62mW stereo class-G headphone driver with 108dB dynamic range and 600µA/channel quiescent current.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Parallel gain enhancement technique for switched-capacitor circuits.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Blind background calibration of harmonic distortion based on selective sampling.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 10-b Ternary SAR ADC With Quantization Time Information Utilization.
IEEE J. Solid State Circuits, 2012

Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Correlated jitter sampling for jitter cancellation in pipelined TDC.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A 10b Ternary SAR ADC with decision time quantization based redundancy.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Asynchronous CLS for Zero Crossing based Circuits.
Proceedings of the 17th IEEE International Conference on Electronics, 2010


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