Harindranath Parameswaran

According to our database1, Harindranath Parameswaran authored at least 7 papers between 2006 and 2012.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

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PhD thesis 
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Links

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Bibliography

2012
Efficient reduction techniques for statistical model generation of standard cells.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
Improved Timing Windows Overlap Check Using Statistical Timing Analysis.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2008
Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Computation of Waveform Sensitivity Using Geometric Transforms for SSTA.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Crosstalk analysis using reconvergence correlation.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Design Partitioning for Reducing Crosstalk Analysis Time.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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