Hariharan Sankaran

According to our database1, Hariharan Sankaran authored at least 10 papers between 2005 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2011
Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2009
Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
High-Level Synthesis Framework for Crosstalk Minimization in VLSI ASICs.
PhD thesis, 2008

A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008

Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2005
Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

System Level Energy Optimization for Location Aware Computing.
Proceedings of the 3rd IEEE International Conference on Pervasive Computing and Communications (PerCom 2005), 2005


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