Hari Vijay Venkatanarayanan

According to our database1, Hari Vijay Venkatanarayanan authored at least 3 papers between 2006 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2008
A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
A Neural Net Branch Predictor to Reduce Power.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006


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