Hari Balachandran

According to our database1, Hari Balachandran authored at least 11 papers between 1996 and 2004.

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Bibliography

2004
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002
Facilitating Rapid First Silicon Debug.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000
Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Computer-aided fault to defect mapping (CAFDM) for defect diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Logic mapping on a microprocessor.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Clustering based techniques for I_DDQ testing.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Correlation of logical failures to a suspect process step.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Expediting ramp-to-volume production.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
On applying non-classical defect models to automated diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1996
Improvement of SRAM-based failure analysis using calibrated Iddq testing.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996


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