Harald Gossner

Orcid: 0000-0002-6280-3613

According to our database1, Harald Gossner authored at least 21 papers between 2001 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016
A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology Mounted in BGA Package.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015
System efficient ESD design.
Microelectron. Reliab., 2015

2012
Electronic design automation (EDA) solutions for ESD-robust design and verification.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2010
System ESD robustness by co-design of on-chip and on-board protection measures.
Microelectron. Reliab., 2010

2009
Do ESD fails in systems correlate with IC ESD robustness?
Microelectron. Reliab., 2009

Reliability aspects of gate oxide under ESD pulse stress.
Microelectron. Reliab., 2009

2007
RF ESD protection strategies: Codesign vs. low-C protection.
Microelectron. Reliab., 2007

A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Circuit design issues in multi-gate FET CMOS technologies.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits.
Microelectron. Reliab., 2005

High abstraction level permutational ESD concept analysis.
Microelectron. Reliab., 2005

2004
ESD protection for the deep sub micron regime - a challenge for design methodology.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003
Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies.
Microelectron. Reliab., 2003

2002
Case study of a technology transfer causing ESD problems.
Microelectron. Reliab., 2002

Device Simulation and Backside Laser Interferometry--Powerful Tools for ESD Protection Development.
Microelectron. Reliab., 2002

2001
Effect of pulse risetime on trigger homogeneity in single finger grounded gate nMOSFET electrostatic discharge protection devices.
Microelectron. Reliab., 2001

Wide range control of the sustaining voltage of electrostatic discharge protection elements realized in a smart power technology.
Microelectron. Reliab., 2001

Advanced 2D/3D ESD device simulation - a powerful tool already used in a pre-Si phase.
Microelectron. Reliab., 2001


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