Haralampos-G. D. Stratigopoulos
Orcid: 0000-0002-9943-5607
According to our database1,
Haralampos-G. D. Stratigopoulos
authored at least 117 papers
between 2003 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
An End-To-End Neuromorphic Radio Classification System With an Efficient Sigma-Delta-Based Spike Encoding Scheme.
IEEE Trans. Artif. Intell., April, 2024
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
A 10.8GS/s, 84MHz-BW RF Bandpass ΣΔ ADC with a 89dB-SFDR and a 62dB-SNDR for LTE/5G Receivers.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Covert Communication Channels Based On Hardware Trojans: Open-Source Dataset and AI-Based Detection.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty: The KDT Resilient Trust Project.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives.
IEEE Des. Test, April, 2023
IEEE Des. Test, April, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
IEEE Trans. Dependable Secur. Comput., 2023
Proceedings of the IEEE European Test Symposium, 2023
Testing and Reliability of Spiking Neural Networks: A Review of the State-of-the-Art.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the IEEE European Test Symposium, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
2016
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs.
J. Electron. Test., 2016
IEEE Des. Test, 2016
IEEE Des. Test, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors.
J. Electron. Test., 2015
Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times.
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 9th International Design and Test Symposium, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
Multidimensional analog test metrics estimation using extreme value theory and statistical blockade.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
IEEE Des. Test Comput., 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Special session 12A: Panel adaptive analog test: Feasibility and opportunities ahead.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 14th IEEE European Test Symposium, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation.
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
2004
J. Electron. Test., 2004
2003
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003