Haoyuan Ying

According to our database1, Haoyuan Ying authored at least 15 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
A novel design and verification framework for low vertical link density 3D network-on-chip based many core embedded systems.
PhD thesis, 2015

NoCDepend: A Flexible and Scalable Dependability Technique for 3D Networks-on-Chip.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-Chip.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Network-on-Chips.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

2013
Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies.
J. Syst. Archit., 2013

GSNoC - The comprehensive design platform for 3-dimensional Networks-on-Chip based many core embedded systems.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systems.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Deadlock-free routing algorithms for 3-dimension Networks-on-Chip with reduced vertical channel density topologies.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

GSNOC UI - A comfortable graphical user interface for advanced design and evaluation of 3-dimensional scalable Networks-on-Chip.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Invited paper: Design criteria for dependable System-on-Chip architectures.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011


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