Haoxing Ren

Orcid: 0000-0003-1028-3860

According to our database1, Haoxing Ren authored at least 101 papers between 2004 and 2024.

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Bibliography

2024
DAG-Aware Synthesis Orchestration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning.
ACM Trans. Design Autom. Electr. Syst., March, 2024

FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware.
CoRR, 2024

CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair.
CoRR, 2024

Intelligent OPC Engineer Assistant for Semiconductor Manufacturing.
CoRR, 2024

Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks.
CoRR, 2024

Differentiable Edge-based OPC.
CoRR, 2024

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool.
CoRR, 2024

Code Less, Align More: Efficient LLM Fine-tuning for Code Generation with Data Pruning.
CoRR, 2024

GOALPlace: Begin with the End in Mind.
CoRR, 2024

Large Language Model (LLM) for Standard Cell Layout Design Optimization.
CoRR, 2024

Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance.
CoRR, 2024

Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Learning to Compare Hardware Designs for High-Level Synthesis.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Challenges for Automating PCB Layout.
Proceedings of the 2024 International Symposium on Physical Design, 2024

MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner.
Proceedings of the 2024 International Symposium on Physical Design, 2024

GPU/ML-Enhanced Large Scale Global Routing Contest.
Proceedings of the 2024 International Symposium on Physical Design, 2024

Novel Transformer Model Based Clustering Method for Standard Cell Design Automation.
Proceedings of the 2024 International Symposium on Physical Design, 2024

ILILT: Implicit Learning of Inverse Lithography Technologies.
Proceedings of the Forty-first International Conference on Machine Learning, 2024

BoolGebra: Attributed Graph-Learning for Boolean Algebraic Manipulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Model.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

DGR: Differentiable Global Router.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Introduction to the Special Issue on Machine Learning for CAD/EDA.
ACM Trans. Design Autom. Electr. Syst., March, 2023

Machine Learning and Algorithms: Let Us Team Up for EDA.
IEEE Des. Test, February, 2023

RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models.
CoRR, 2023

ChipNeMo: Domain-Adapted LLMs for Chip Design.
CoRR, 2023

VerilogEval: Evaluating Large Language Models for Verilog Code Generation.
CoRR, 2023

DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning.
Proceedings of the 2023 International Symposium on Physical Design, 2023

NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model.
Proceedings of the 2023 International Symposium on Physical Design, 2023

AutoDMP: Automated DREAMPlace-based Macro Placement.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Reinforcement Learning Guided Detailed Routing for Custom Circuits.
Proceedings of the 2023 International Symposium on Physical Design, 2023

An Adversarial Active Sampling-Based Data Augmentation Framework for AI-Assisted Lithography Modeling.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Enabling Scalable AI Computational Lithography with Physics-Inspired Models.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

BufFormer: A Generative ML Framework for Scalable Buffering.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design.
CoRR, 2022

Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training.
CoRR, 2022

Placement Optimization via PPA-Directed Graph Clustering.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Embracing Machine Learning in EDA.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus.
Proceedings of the 51st International Conference on Parallel Processing, 2022

Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper).
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TransSizer: A Novel Transformer-Based Fast Gate Sizer.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TAG: Learning Circuit Spatial Embedding from Layouts.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

GATSPI: GPU accelerated gate-level simulation for power improvement.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Generic lithography modeling with dual-band optics-inspired neural networks.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Generative self-supervised learning for gate sizing: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning.
CoRR, 2021

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking.
CoRR, 2021

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference.
CoRR, 2021

Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic Rewriting.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Accelerating Chip Design With Machine Learning.
IEEE Micro, 2020

MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification.
CoRR, 2020

ML for CAD - Where is the Treasure Hiding?
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Toward Intelligent Physical Design: Deep Learning and GPU Acceleration.
Proceedings of the 2019 International Symposium on Physical Design, 2019

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

PRIMAL: Power Inference using Machine Learning.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

High Performance Graph Convolutional Networks with Applications in Testability Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
RouteNet: routability prediction for mixed-size designs using convolutional neural network.
Proceedings of the International Conference on Computer-Aided Design, 2018

2014
A brief introduction on contemporary High-Level Synthesis.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013
Network flow based datapath bit slicing.
Proceedings of the International Symposium on Physical Design, 2013

LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Intuitive ECO synthesis for high performance circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Design methodology for the IBM POWER7 microprocessor.
IBM J. Res. Dev., 2011

2010
Logical and physical restructuring of fan-in trees.
Proceedings of the 2010 International Symposium on Physical Design, 2010

History-based VLSI legalization using network flow.
Proceedings of the 47th Design Automation Conference, 2010

2009
Low cost test point insertion without using extra registers for high performance design.
Proceedings of the 2009 IEEE International Test Conference, 2009

DeltaSyn: An efficient logic difference optimizer for ECO synthesis.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Timing-Driven Placement.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Placement-Driven Synthesis Design Closure Tool.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

2007
Diffusion-Based Placement Migration With Application on Legalization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Techniques for Fast Physical Synthesis.
Proc. IEEE, 2007

The nuts and bolts of physical synthesis.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
Proceedings of the 44th Design Automation Conference, 2007

Hippocrates: First-Do-No-Harm Detailed Placement.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2005
Sensitivity guided net weighting for placement-driven synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Computational geometry based placement migration.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Diffusion-based placement migration.
Proceedings of the 42nd Design Automation Conference, 2005

2004
True crosstalk aware incremental placement with noise map.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004


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