Haoxing Ren
Orcid: 0000-0003-1028-3860
According to our database1,
Haoxing Ren
authored at least 101 papers
between 2004 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning.
ACM Trans. Design Autom. Electr. Syst., March, 2024
FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware.
CoRR, 2024
CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair.
CoRR, 2024
Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks.
CoRR, 2024
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool.
CoRR, 2024
Code Less, Align More: Efficient LLM Fine-tuning for Code Generation with Data Pruning.
CoRR, 2024
Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance.
CoRR, 2024
Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
Proceedings of the 2024 International Symposium on Physical Design, 2024
Proceedings of the 2024 International Symposium on Physical Design, 2024
Proceedings of the 2024 International Symposium on Physical Design, 2024
Proceedings of the 2024 International Symposium on Physical Design, 2024
Proceedings of the Forty-first International Conference on Machine Learning, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
ACM Trans. Design Autom. Electr. Syst., March, 2023
IEEE Des. Test, February, 2023
CoRR, 2023
CoRR, 2023
DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning.
Proceedings of the 2023 International Symposium on Physical Design, 2023
NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model.
Proceedings of the 2023 International Symposium on Physical Design, 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
An Adversarial Active Sampling-Based Data Augmentation Framework for AI-Assisted Lithography Modeling.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design.
CoRR, 2022
Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training.
CoRR, 2022
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022
Proceedings of the 51st International Conference on Parallel Processing, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning.
CoRR, 2021
CoRR, 2021
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference.
CoRR, 2021
Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Proceedings of the 2019 International Symposium on Physical Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
High Performance Graph Convolutional Networks with Applications in Testability Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
RouteNet: routability prediction for mixed-size designs using convolutional neural network.
Proceedings of the International Conference on Computer-Aided Design, 2018
2014
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
2013
Proceedings of the International Symposium on Physical Design, 2013
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2011
2010
Proceedings of the 2010 International Symposium on Physical Design, 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
Low cost test point insertion without using extra registers for high performance design.
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
2008
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004