Haorui Luo

Orcid: 0000-0001-5007-3142

According to our database1, Haorui Luo authored at least 6 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
An Efficient Transistor-Model-Assisted Layout Synthesis Approach Using Improved Implicit Space Mapping for High-Performance MMIC PAs.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

2023
A Compact 1.0-12.5-GHz LNA MMIC With 1.5-dB NF Based on Multiple Resistive Feedback in 0.15-μm GaAs pHEMT Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

A 9-to-42-GHz High-Gain Low-Noise Amplifier Using Coupled Interstage Feedback in 0.15-μm GaAs pHEMT Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

A Rapid Matching Network Layout Synthesis and Optimization Method for High-Performance MMIC PAs Using Modified Implicit Space Mapping.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

2022
Design and Analysis of a Cascode Distributed LNA With Gain and Noise Improvement in 0.15-μm GaAs pHEMT Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2019
Fast and Accurate Temperature-Dependent Current Modeling of HBTs Using the Dimension Reduction Method.
IEEE Access, 2019


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