Haolin Han

According to our database, Haolin Han authored at least 8 papers between 2019 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Rapid digital background calibration of bit weights in pipelined SAR ADC based on multi-PN injection.

Le Chen, Yi Shen, Ruixue Ding, Shubin Liu, Haolin Han

Microelectron. J., 2025

2024

A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC.

Haolin Han, Shubin Liu, Hongzhi Liang, Yi Shen, Jianyu Guo, Ruili Ren, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique.

Haolin Han, Jinwei Zhang, Ruili Ren, Yi Shen, Shubin Liu, Ruixue Ding

Microelectron. J., 2024

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry.

Haolin Han, Ruili Ren, Yi Shen, Ruixue Ding, Shubin Liu, Hongzhi Liang

Microelectron. J., 2024

2023

A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.

Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 0.012mm² 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply.

Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Hongzhi Liang, Haolin Han, Menghao Wang, Weijie Han, Zhangming Zhu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2020

A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier.

Shubin Liu, Haolin Han, Yi Shen, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019

Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC.

Shubin Liu, Haolin Han, Ruixue Ding

J. Circuits Syst. Comput., 2019