Haochang Chen

Orcid: 0000-0001-6196-4418

According to our database1, Haochang Chen authored at least 12 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Two-Stage Interpolation Time-to-Digital Converter Implemented in 20 and 28 nm FGPAs.
IEEE Trans. Ind. Electron., November, 2024

2023
Low-Hardware Consumption, Resolution-Configurable Gray Code Oscillator Time-to-Digital Converters Implemented in 16 nm, 20 nm, and 28 nm FPGAs.
IEEE Trans. Ind. Electron., 2023

2022
128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations.
IEEE Trans. Ind. Electron., 2022

Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods.
IEEE Trans. Ind. Electron., 2022

Multichannel Time-to-Digital Converters With Automatic Calibration in Xilinx Zynq-7000 FPGA Devices.
IEEE Trans. Ind. Electron., 2022

Assessing Novel Lidar Modalities for Maximizing Coverage of a Spaceborne System through the Use of Diode Lasers.
Remote. Sens., 2022

Low hardware consumption, resolution-configurable Gray code oscillator time-to-digital converters implemented in 16nm, 20nm and 28nm FPGAs.
CoRR, 2022

2020
Multi-channel high-linearity time-to-digital converters in 20 nm and 28 nm FPGAs for LiDAR applications.
Proceedings of the 6th International Conference on Event-Based Control, 2020

2019
Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs.
IEEE Trans. Ind. Electron., 2019

A $192\times128$ Time Correlated SPAD Image Sensor in 40-nm CMOS Technology.
IEEE J. Solid State Circuits, 2019

2018
A 192×128 Time Correlated Single Photon Counting Imager in 40nm CMOS Technology.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
A Low Nonlinearity, Missing-Code Free Time-to-Digital Converter Based on 28-nm FPGAs With Embedded Bin-Width Calibrations.
IEEE Trans. Instrum. Meas., 2017


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