Hao Zheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

Inferring Message Flows From System Communication Traces.

[BibT_eX]

[DOI]

CoRR, 2024

A Multi-Expert Large Language Model Architecture for Verilog Code Generation.

[BibT_eX]

[DOI]

CoRR, 2024

Rare-Event Guided Analysis of Infinite-State Chemical Reaction Networks.

[BibT_eX]

[DOI]

Proceedings of the Quantitative Evaluation of Systems and Formal Modeling and Analysis of Timed Systems, 2024

2023

STAMINA in C++: Modernizing an Infinite-State Probabilistic Model Checker.

[BibT_eX]

[DOI]

Proceedings of the Quantitative Evaluation of Systems - 20th International Conference, 2023

System-on-Chip Message Flow Mining with Masked-Language Models.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

Mining Patterns From Concurrent Execution Traces.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Mining SoC Message Flows with Attention Model.

[BibT_eX]

[DOI]

CoRR, 2022

Counterexample Generation for Infinite-State Chemical Reaction Networks.

[BibT_eX]

[DOI]

CoRR, 2022

Deep Bidirectional Transformers for SoC Flow Specification Mining.

[BibT_eX]

[DOI]

CoRR, 2022

2021

Tools and Algorithms for SoC Communication Traces.

[BibT_eX]

[DOI]

CoRR, 2021

Model Synthesis for Communication Traces of System-on-Chip Designs.

[BibT_eX]

[DOI]

CoRR, 2021

A Comparative Study of Specification Mining Methods for SoC Communication Traces.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Mining Message Flows from System-on-Chip Execution Traces.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Model Synthesis for Communication Traces of System Designs.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.

[BibT_eX]

[DOI]

CoRR, 2020

Local State Space Analysis to Assist Partial Order Reduction.

[BibT_eX]

[DOI]

Yingying Zhang

Vishalini Laguduva Ramnath

CoRR, 2020

Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A Distributed Framework for Real Time Object Detection at Low Frame Rates with IoT Edge Nodes.

[BibT_eX]

[DOI]

Lakshmi Kavya Kalyanam

Srinivas Katkoori

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

Stream-Monitoring Automata.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Software and Computer Applications, 2020

2019

Approximation Techniques for Stochastic Analysis of Biological Systems.

[BibT_eX]

[DOI]

Proceedings of the Automated Reasoning for Systems Biology and Medicine, 2019

Approximation Techniques for Stochastic Analysis of Biological Systems.

[BibT_eX]

[DOI]

CoRR, 2019

A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug.

[BibT_eX]

[DOI]

Yuting Cao

Sandip Ray

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

STAMINA: STochastic Approximate Model-Checker for INfinite-State Analysis.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 31st International Conference, 2019

2018

Enhancing Observability for Post-Silicon Debug with On-chip Communication Monitors.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

POSTER: Towards Precise and Automated Verification of Security Protocols in Coq.

[BibT_eX]

[DOI]

Hernan M. Palombo

Jay Ligatti

Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

2016

An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis.

[BibT_eX]

[DOI]

Sci. Comput. Program., 2016

Protocol-guided analysis of post-silicon traces under limited observability.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

Compositional Model Checking of Concurrent Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

2014

Local State Space Analysis Leads to Better Partial Order Reduction.

[BibT_eX]

[DOI]

Yingying Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Local state space construction for compositional verification of concurrent systems.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Model Checking of Software, 2014

Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods for Industrial Critical Systems, 2014

2012

A Compositional Minimization Approach for Large Asynchronous Design Verification.

[BibT_eX]

[DOI]

Proceedings of the Model Checking Software - 19th International Workshop, 2012

An Improvement in Partial Order Reduction Using Behavioral Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Poster Abstract: Methods and Tools for Verification of Cyber-Physical Systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems, 2012

Using decision diagrams to compactly represent the state space for explicit model checking.

[BibT_eX]

[DOI]

Andrew Price

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

2011

A Behavioral Analysis Approach for Efficient Partial Order Reduction.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on High-Assurance Systems Engineering, 2011

2010

Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement.

[BibT_eX]

[DOI]

Tomohiro Yoneda

IEEE Trans. Computers, 2010

Automatic abstraction for verification of cyber-physical systems.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 1st International Conference on Cyber-Physical Systems, 2010

State space reductions for scalable verification of asynchronous designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2009

Automated Interface Refinement for Compositional Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs.

[BibT_eX]

[DOI]

Tomohiro Yoneda

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008

A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification.

[BibT_eX]

[DOI]

Jared Ahrens

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

Timing Jitter Characterization for Mixed-Signal Production Test Using the Interpolation Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2007

2006

Verification of timed circuits with failure-directed abstractions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Data Dependent Jitter Characterization Based on Fourier Analysis.

[BibT_eX]

[DOI]

Di Mu

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005

Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Characterizing the VCO jitter due to the digital simultaneous switching noise.

[BibT_eX]

[DOI]

Peilin Song

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2003

Modular verification of timed circuits using automatic abstraction.

[BibT_eX]

[DOI]

Eric Mercer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2001

Automatic Abstraction for Verification of Timed Circuits and Systems.

[BibT_eX]

[DOI]

Eric Mercer

Proceedings of the Computer Aided Verification, 13th International Conference, 2001

Timed circuits: a new paradigm for high-speed design.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

1999

Architectural Synthesis of Timed Asynchronous Systems.

[BibT_eX]

[DOI]

Brandon M. Bachman

Proceedings of the IEEE International Conference On Computer Design, 1999

1997

An asynchronous implementation of the maxlist algorithm.

[BibT_eX]

[DOI]