Hao Xu
Orcid: 0000-0002-0044-1231Affiliations:
- University of California at Los Angeles, Electrical Engineering Department, CA, USA
According to our database1,
Hao Xu
authored at least 19 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024
A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier.
IEEE J. Solid State Circuits, October, 2023
A 6-12 GHz Wideband Low-Noise Amplifier With 0.8-1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.
IEEE J. Solid State Circuits, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
2021
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW.
Proceedings of the 47th ESSCIRC 2021, 2021
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2015
IEEE J. Solid State Circuits, 2015
2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014