Hao-Wei Hung

According to our database, Hao-Wei Hung authored at least 8 papers between 2011 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.

Jay Im, Kevin Zheng, Chuen-Huei Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang

IEEE J. Solid State Circuits, 2021

2020

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.

Jay Im, Kevin Zheng, Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2015

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology.

Ping-Chuan Chiang, Jhih-Yu Jiang, Hao-Wei Hung, Chin-Yang Wu, Gaun-Sing Chen, Jri Lee

IEEE J. Solid State Circuits, 2015

2014

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS.

Ping-Chuan Chiang, Hao-Wei Hung, Hsiang-Yun Chu, Guan-Sing Chen, Jri Lee

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology.

Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

100Gb/s ethernet chipsets in 65nm CMOS technology.

Jhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology.

Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

IEEE J. Solid State Circuits, 2012

2011

A 40Gb/s TX and RX chip set in 65nm CMOS.

Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2011