Hao Chen

According to our database, Hao Chen authored at least 11 papers between 2012 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2020

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices.

Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang

Proceedings of the IEEE International Test Conference, 2020

Novel Circuit Probing for Tiny Inductor.

Chia-Heng Tsai, Chi-Chang Lai, Hao Chen, Min-Jer Wang

Proceedings of the IEEE International Test Conference in Asia, 2020

Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill.

Mincent Lee, Cheng-Tse Lu, Chia-Heng Tsai, Hao Chen, Min-Jer Wang

Proceedings of the IEEE International Test Conference in Asia, 2020

2019

High Quality Test Methodology for Highly Reliable Devices.

Hao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang

Proceedings of the IEEE International Test Conference, 2019

2017

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package.

Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

IEEE Des. Test, 2017

Fan-out wafer level chip scale package testing.

Hao Chen, Hung-Chih Lin, Min-Jer Wang

Proceedings of the International Test Conference in Asia, 2017

2016

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package.

Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 53rd Annual Design Automation Conference, 2016

2014

A novel DFT architecture for 3DIC test, diagnosis and repair.

Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Wafer Level Chip Scale Package copper pillar probing.

Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 2014 International Test Conference, 2014

2013

Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch.

Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 2013 IEEE International Test Conference, 2013

2012

A memory yield improvement scheme combining built-in self-repair and error correction codes.

Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 2012 IEEE International Test Conference, 2012