Hao Chen

Affiliations:
  • Taiwan Semiconductor Manufacturing Company, Ltd, Hsinchu, Taiwan


According to our database1, Hao Chen authored at least 11 papers between 2012 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices.
Proceedings of the IEEE International Test Conference, 2020

Novel Circuit Probing for Tiny Inductor.
Proceedings of the IEEE International Test Conference in Asia, 2020

Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill.
Proceedings of the IEEE International Test Conference in Asia, 2020

2019
High Quality Test Methodology for Highly Reliable Devices.
Proceedings of the IEEE International Test Conference, 2019

2017
Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package.
IEEE Des. Test, 2017

Fan-out wafer level chip scale package testing.
Proceedings of the International Test Conference in Asia, 2017

2016
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2014
A novel DFT architecture for 3DIC test, diagnosis and repair.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Wafer Level Chip Scale Package copper pillar probing.
Proceedings of the 2014 International Test Conference, 2014

2013
Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch.
Proceedings of the 2013 IEEE International Test Conference, 2013

2012
A memory yield improvement scheme combining built-in self-repair and error correction codes.
Proceedings of the 2012 IEEE International Test Conference, 2012


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