Hao Cai

According to our database, Hao Cai authored at least 109 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication.

Bo Liu, Na Xie, Qingwen Wei, Guang Yang, Chonghang Xie, Weiqiang Liu, Hao Cai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

Layer-Wise Mixed-Modes CNN Processing Architecture With Double-Stationary Dataflow and Dimension-Reshape Strategy.

Bo Liu, Xinxiang Huang, Yang Zhang, Guang Yang, Han Yan, Chen Zhang, Zejv Li, Yuanhao Wang, Hao Cai

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024

Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application.

Xin Chen, Yuxin Bai, Hao Cai, Congyi Zhu, Xinjie Zhou, Ying Zhang, Weiqiang Liu

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024

Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications.

Zeju Li, Qinfan Wang, Zihan Zou, Qiao Shen, Na Xie, Hao Cai, Hao Zhang, Bo Liu

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

On-Chip-Registration Supported ASR Processor Using Two-Step Transfer-Learning TWN.

Bo Liu, Xuanhao Zhang, Hui Kou, Chenjie Xia, Zhen Wang, Hao Cai

IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

Intrinsic MRAM Properties Enable Security Circuits.

Haoran Du, You Wang, Jun Yang, Hao Cai

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits.

Yu Gong, Bo Liu, Hao Cai, Longxing Shi, Weiqiang Liu

IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.

Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference.

Jia-Le Cui, Yanan Guo, Juntong Chen, Bo Liu, Hao Cai

IEEE Trans. Emerg. Top. Comput., 2024

Towards Reliability MRAM for Energy-Efficient Spin-orbit Torque Switching.

Zhenghan Fang, Lirida Naviner, Wen Wang, Wei Le, Hao Cai

Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.

An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory.

Rong Zhou, Bo Liu, Xin Si, Hao Cai

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Live Demonstration: A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing.

Chenjie Xia, Xuanhao Zhang, Zihan Zou, Hao Cai, Bo Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Small-Footprint Automatic Speech Recognition System using Two-Stage Transfer Learning based Symmetrized Ternary Weight Network.

Xuanhao Zhang, Hui Kou, Chenjie Xia, Hao Cai, Bo Liu

Proceedings of the IEEE International Conference on Acoustics, 2024

FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow.

Bo Liu, Qingwen Wei, Yang Zhang, Xingyu Xu, Zihan Zou, Xinxiang Huang, Xin Si, Hao Cai

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Truly Random Number Generation by Using in-Plane Magnetic Tunnel Junction with Weak Anisotropy.

You Wang, Chaoyue Zhang, Yefan Xu, Yu Gong, Hao Cai, Weiqiang Liu

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2024

2023

W-AMA: Weight-aware Approximate Multiplication Architecture for neural processing.

Bo Liu, Renyuan Zhang, Qiao Shen, Zeju Li, Na Xie, Yuanhao Wang, Chonghang Xie, Hao Cai

Comput. Electr. Eng., October, 2023

Computing in-memory with cascaded spintronic devices for AI edge.

Zhong-Jian Bian, Bo Liu, Hao Cai

Comput. Electr. Eng., August, 2023

Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition.

Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Renyuan Zhang, Yu Gong, Zhen Wang, Wei Ge, Jun Yang

IEEE Des. Test, June, 2023

Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms.

Hao Cai, Yaoru Hou, Mengdi Zhang, Bo Liu, Lirida Alves de Barros Naviner

IEEE Des. Test, June, 2023

AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS.

Weiwei Shan, Junyi Qian, Lixuan Zhu, Jun Yang, Cheng Huang, Hao Cai

IEEE J. Solid State Circuits, March, 2023

A Survey of MRAM-Centric Computing: From Near Memory to In Memory.

Yueting Li, Tianshuo Bai, Xinyi Xu, Yundong Zhang, Bi Wu, Hao Cai, Biao Pan, Weisheng Zhao

IEEE Trans. Emerg. Top. Comput., 2023

A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment.

Bo Liu, Anfeng Xue, Ziyu Wang, Na Xie, Xuetao Wang, Zhen Wang, Hao Cai

IEEE Trans. Circuits Syst. II Express Briefs, 2023

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.

An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.

Hao Cai, Zhong-Jian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A FinFET Integrated STT-MRAM with Triple Balanced Access Strategy.

Xinshu Xie, Jiongzhe Su, Hao Zhang, Hao Cai

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis.

Qingwen Wei, Yang Zhang, Xingyu Xu, Hao Cai, Bo Liu

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Spice-Compatible Modeling of Double Barrier MTJ for Highly Reliable Circuits.

You Wang, Yefan Xu, Chaoyue Zhang, Yu Gong, Hao Cai, Weiqiang Liu

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Temperature-Adaptive MRAM Sensing Using Varied Magneto-Resistance.

Jiongzhe Su, Hao Zhang, Hao Cai

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs.

Xingyu Xu, Qingwen Wei, Yang Zhang, Hao Cai, Bo Liu

Proceedings of the International Conference on Compilers, 2023

2022

Writing-only in-MRAM computing paradigm for ultra-low power applications.

Bo Liu, Mingyue Liu, Yongliang Zhou, Xiaofeng Hong, Hao Cai, Lirida Alves de Barros Naviner

Microprocess. Microsystems, April, 2022

A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM.

Rashid Ali, Deming Zhang, Hao Cai, Weisheng Zhao, You Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network.

Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Ziyu Wang, Yu Gong, Weiqiang Liu, Jinjiang Yang, Zhen Wang, Jun Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Quality Driven Systematic Approximation for Binary-Weight Neural Network Deployment.

Yu Gong, Hao Cai, Haige Wu, Wei Ge, Hao Yan, Zhen Wang, Longxing Shi, Bo Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell.

Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing.

Bo Liu, Ziyu Wang, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Qiao Shen, Na Xie, Yu Gong, Zhen Wang, Jun Yang, Hao Cai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Bit-error-rate aware sensing-error correction interaction in spintronic MRAM.

Hao Cai, Xinfang Tong, Pengcheng Wu, Xinning Liu, Bo Liu

J. Syst. Archit., 2022

Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing.

Bo Liu, Zilong Zhang, Hao Cai, Reyuan Zhang, Zhen Wang, Jun Yang

Sci. China Inf. Sci., 2022

Low-cost stochastic number generator based on MRAM for stochastic computing.

You Wang, Bi Wu, Hao Cai, Weiqiang Liu

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

A Low Power DNN-based Speech Recognition Processor with Precision Recoverable Approximate Computing.

Bo Liu, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Ziyu Wang, Haige Wu, Hao Cai

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A TWN Inspired Speaker Verification Processor with Hardware-friendly Weight Quantization.

Xuanhao Zhang, Haige Wu, Renyuan Zhang, Zihang Xu, Hao Zhang, Bo Liu, Hao Cai

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A CGP-based Efficient Approximate Multiplier with Error Compensation.

Qiao Shen, Renyuan Zhang, Hao Zhang, Hao Cai, Bo Liu, Jian Xiao

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing.

Bo Liu, Hao Cai, Xuan Zhang, Haige Wu, Anfeng Xue, Zilong Zhang, Zhen Wang, Jun Yang

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Triple-Skipping Near-MRAM Computing Framework for AIoT Era.

Juntong Chen, Hao Cai, Bo Liu, Jun Yang

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Approximate Computing for Energy-Constrained DNN-Based Speech Recognition.

Bo Liu, Hao Cai, Zhen Wang, Jun Yang

Proceedings of the Approximate Computing, 2022

Spintronic Solutions for Approximate Computing.

You Wang, Hao Cai, Kaili Zhang, Bo Wu, Bo Liu, Deming Zhang, Weisheng Zhao

Proceedings of the Approximate Computing, 2022

2021

Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration.

Hao Cai, Juntong Chen, Yongliang Zhou, Weisheng Zhao

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS.

Weiwei Shan, Minhao Yang, Tao Wang, Yicheng Lu, Hao Cai, Lixuan Zhu, Jiaming Xu, Chengjun Wu, Longxing Shi, Jun Yang

IEEE J. Solid State Circuits, 2021

A survey of in-spin transfer torque MRAM computing.

Hao Cai, Bo Liu, Juntong Chen, Lirida A. B. Naviner, Yongliang Zhou, Zhen Wang, Jun Yang

Sci. China Inf. Sci., 2021

Hybrid MTJ-CMOS Integration for Sigma-Delta ADC.

Yu-ang Wu, Lirida A. B. Naviner, Hao Cai

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Cryogenic In-MRAM Computing.

Yaoru Hou, We Ge, Yanan Guo, Lirida A. B. Naviner, You Wang, Bo Liu, Jun Yang, Hao Cai

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

In-MRAM Computing Elements with Single-Step Convolution and Fully Connected for BNN/TNN.

Zhong-Jian Bian, Yanan Guo, Bo Liu, Hao Cai

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition.

Bo Liu, Zeyu Shen, Lepeng Huang, Yu Gong, Zilong Zhang, Hao Cai

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM.

You-You Zhang, Lirida A. B. Naviner, Hao Cai

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.

Yongliang Zhou, Hao Cai, Lei Xie, Menglin Han, Mingyue Liu, Shi Xu, Bo Liu, Weisheng Zhao, Jun Yang

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.

Yongliang Zhou, Hao Cai, Bo Liu, Weisheng Zhao, Jun Yang

IEEE Trans. Circuits Syst., 2020

A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor.

Bo Liu, Hao Cai, Zhen Wang, Yuhao Sun, Zeyu Shen, Wentao Zhu, Yan Li, Yu Gong, Wei Ge, Jun Yang, Longxing Shi

IEEE Trans. Circuits Syst., 2020

Magnetic Tunnel Junction Applications.

Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner, Yongliang Zhou, Hao Cai

Sensors, 2020

TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS.

Weiwei Shan, Wentao Dai, Chuan Zhang, Hao Cai, Peiye Liu, Jun Yang, Longxing Shi

IEEE J. Solid State Circuits, 2020

Towards an automated design flow for memristor based VLSI circuits.

Lei Xie, Hao Cai, Chao Wang, Jun Yang

Integr., 2020

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.

Hao Cai, Honglan Jiang, Yongliang Zhou, Menglin Han, Bo Liu

CCF Trans. High Perform. Comput., 2020

Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing.

Bo Liu, Hao Cai, Yu Gong, Wentao Zhu, Yan Li, Wei Ge, Zhen Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Magnetic Tunnel Junction-based Analog-to-Digital Converter using Spin Orbit Torque Mechanism.

Nilson Maciel, Elaine Crespo Marques, Lírida A. B. Naviner, Hao Cai

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing.

Bo Liu, Yan Li, Lepeng Huang, Hao Cai, Wentao Zhu, Shisheng Guo, Yu Gong, Zhen Wang

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Modeling Attack Resilient Physical Unclonable Function Based on STT-MRAM.

Zhengyi Hou, You Wang, Deming Zhang, Chengzhi Wang, Hao Cai

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN.

Bo Liu, Yuhao Sun, Hao Cai, Zeyu Shen, Yu Gong, Lepeng Huang, Zhen Wang

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS.

Weiwei Shan, Xinchao Shang, Xing Wan, Hao Cai, Chuan Zhang, Jun Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration.

Hao Cai, You Wang, Lirida Alves de Barros Naviner, Xinning Liu, Weiwei Shan, Jun Yang, Weisheng Zhao

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Review of Sparse Recovery Algorithms.

Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang

IEEE Access, 2019

Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery.

Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement.

Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu, Jun Yang

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing.

Lei Xie, Hao Cai, Jun Yang

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM.

Mingyue Liu, Hao Cai, Menglin Han, Lei Xie, Jun Yang, Lirida A. B. Naviner

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.

Hao Cai, Honglan Jiang, Menglin Han, Zhaohao Wang, You Wang, Jun Yang, Jie Han, Leibo Liu, Weisheng Zhao

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Deep Learning Approaches for Sparse Recovery in Compressive Sensing.

Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang

Proceedings of the 11th International Symposium on Image and Signal Processing and Analysis, 2019

Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.

Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs.

Wentao Dai, Weiwei Shan, Xinchao Shang, Xinning Liu, Hao Cai, Jun Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology.

Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner, Hao Cai

Microelectron. Reliab., 2018

A high-reliability and low-power computing-in-memory implementation within STT-MRAM.

Liuyang Zhang, Erya Deng, Hao Cai, You Wang, Lionel Torres, Aida Todri-Sanial, Youguang Zhang

Microelectron. J., 2018

A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.

Liuyang Zhang, Wang Kang, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

MRAM-on-FDSOI Integration: A Bit-Cell Perspective.

Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques.

Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Weiwei Shan, Jun Yang, Weisheng Zhao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Compressed Sensing for Wideband HF Channel Estimation.

Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang

Proceedings of the 4th International Conference on Frontiers of Signal Processing, 2018

Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.

You Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, Lirida A. B. Naviner

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power.

Hao Cai, Menglin Han, You Wang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement.

Menglin Han, Hao Cai, Jun Yang, Lirida A. B. Naviner, You Wang, Weisheng Zhao

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology.

Hao Cai, You Wang, Lirida Alves de Barros Naviner, Weisheng Zhao

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core.

Hao Cai, You Wang, Lirida A. B. Naviner, Weisheng Zhao

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.

Hao Cai, You Wang, Lirida A. B. Naviner, Wang Kang, Weisheng Zhao

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.

You Wang, Hao Cai, Lirida A. B. Naviner, Xiaoxuan Zhao, Yue Zhang, Mariem Slimani, Jacques-Olivier Klein, Weisheng Zhao

Microelectron. Reliab., 2016

Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters.

Mariem Slimani, Paulo F. Butzen, Lirida A. B. Naviner, You Wang, Hao Cai

Microelectron. Reliab., 2016

Efficient reliability evaluation methodologies for combinational circuits.

Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner, You Wang, Mariem Slimani, Jean-François Naviner

Microelectron. Reliab., 2016

A novel circuit design of true random number generator using magnetic tunnel junction.

You Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Approximate computing in MOS/spintronic non-volatile full-adder.

Hao Cai, You Wang, Lirida A. B. Naviner, Zhaohao Wang, Weisheng Zhao

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

2015

Compact thermal modeling of spin transfer torque magnetic tunnel junction.

You Wang, Hao Cai, Lirida A. B. Naviner, Yue Zhang, Jacques-Olivier Klein, Weisheng Zhao

Microelectron. Reliab., 2015

A dual-rail compact defect-tolerant multiplexer.

Arwa Ben Dhia, Mariem Slimani, Hao Cai, Lirida A. B. Naviner

Microelectron. Reliab., 2015

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology.

Hao Cai, You Wang, Lirida A. B. Naviner, W. S. Zhao

Microelectron. Reliab., 2015

Cross-layer investigation of continuous-time sigma-delta modulator under aging effects.

Hao Cai, You Wang, Kaikai Liu, Lirida Alves de Barros Naviner, Hervé Petit, Jean-François Naviner

Microelectron. Reliab., 2015

Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method.

Ting An, Kaikai Liu, Hao Cai, Lirida A. B. Naviner

Microelectron. Reliab., 2015

Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction.

Lirida Alves de Barros Naviner, Hao Cai, You Wang, Weisheng Zhao, Arwa Ben Dhia

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2014

Reliability-aware delay faults evaluation of CMOS flip-flops.

Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner

Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Efficient implementation for accurate analysis of CED circuits against multiple faults.

Ting An, Kaikai Liu, Hao Cai, Lirida Alves de Barros Naviner

Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Simulation study of aging in CMOS binary adders.

Ting An, Hao Cai, Lirida Alves de Barros Naviner

Proceedings of the 37th International Convention on Information and Communication Technology, 2014

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix.

Lirida A. B. Naviner, Kaikai Liu, Hao Cai, Jean-François Naviner

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013

A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts.

Hao Cai, Hervé Petit, Jean-François Naviner

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology.

Kaikai Liu, Ting An, Hao Cai, Lirida A. B. Naviner, Jean-François Naviner, Hervé Petit

Proceedings of Eurocon 2013, 2013

Reliability analysis of combinational circuits with the influences of noise and single-event transients.

Kaikai Liu, Hao Cai, Ting An, Lirida A. B. Naviner, Jean-François Naviner, Hervé Petit

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems.

Hao Cai, Hervé Petit, Jean-François Naviner

J. Low Power Electron., 2012

2011

Reliability aware design of low power continuous-time sigma-delta modulator.

Hao Cai, Hervé Petit, Jean-François Naviner

Microelectron. Reliab., 2011