Hao Cai

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

Layer-Wise Mixed-Modes CNN Processing Architecture With Double-Stationary Dataflow and Dimension-Reshape Strategy.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024

Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024

Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

On-Chip-Registration Supported ASR Processor Using Two-Step Transfer-Learning TWN.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

Intrinsic MRAM Properties Enable Security Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2024

Towards Reliability MRAM for Energy-Efficient Spin-orbit Torque Switching.

[BibT_eX]

[DOI]

Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Live Demonstration: A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Small-Footprint Automatic Speech Recognition System using Two-Stage Transfer Learning based Symmetrized Ternary Weight Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2024

FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Truly Random Number Generation by Using in-Plane Magnetic Tunnel Junction with Weak Anisotropy.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2024

2023

W-AMA: Weight-aware Approximate Multiplication Architecture for neural processing.

[BibT_eX]

[DOI]

Comput. Electr. Eng., October, 2023

Computing in-memory with cascaded spintronic devices for AI edge.

[BibT_eX]

[DOI]

Zhong-Jian Bian

Bo Liu

Comput. Electr. Eng., August, 2023

Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition.

[BibT_eX]

[DOI]

IEEE Des. Test, June, 2023

Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms.

[BibT_eX]

[DOI]

IEEE Des. Test, June, 2023

AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, March, 2023

A Survey of MRAM-Centric Computing: From Near Memory to In Memory.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2023

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A FinFET Integrated STT-MRAM with Triple Balanced Access Strategy.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Spice-Compatible Modeling of Double Barrier MTJ for Highly Reliable Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Temperature-Adaptive MRAM Sensing Using Varied Magneto-Resistance.

[BibT_eX]

[DOI]

Jiongzhe Su

Hao Zhang

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2023

2022

Writing-only in-MRAM computing paradigm for ultra-low power applications.

[BibT_eX]

[DOI]

Microprocess. Microsystems, April, 2022

A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Quality Driven Systematic Approximation for Binary-Weight Neural Network Deployment.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Bit-error-rate aware sensing-error correction interaction in spintronic MRAM.

[BibT_eX]

[DOI]

J. Syst. Archit., 2022

Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2022

Low-cost stochastic number generator based on MRAM for stochastic computing.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

A Low Power DNN-based Speech Recognition Processor with Precision Recoverable Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A TWN Inspired Speaker Verification Processor with Hardware-friendly Weight Quantization.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A CGP-based Efficient Approximate Multiplier with Error Compensation.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Triple-Skipping Near-MRAM Computing Framework for AIoT Era.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Approximate Computing for Energy-Constrained DNN-Based Speech Recognition.

[BibT_eX]

[DOI]

Proceedings of the Approximate Computing, 2022

Spintronic Solutions for Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the Approximate Computing, 2022

2021

Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

A survey of in-spin transfer torque MRAM computing.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2021

Hybrid MTJ-CMOS Integration for Sigma-Delta ADC.

[BibT_eX]

[DOI]

Yu-ang Wu

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Cryogenic In-MRAM Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

In-MRAM Computing Elements with Single-Step Convolution and Fully Connected for BNN/TNN.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM.

[BibT_eX]

[DOI]

You-You Zhang

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Magnetic Tunnel Junction Applications.

[BibT_eX]

[DOI]

Nilson Maciel

Yongliang Zhou

Sensors, 2020

TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

Towards an automated design flow for memristor based VLSI circuits.

[BibT_eX]

[DOI]

Integr., 2020

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.

[BibT_eX]

[DOI]

CCF Trans. High Perform. Comput., 2020

Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Magnetic Tunnel Junction-based Analog-to-Digital Converter using Spin Orbit Torque Mechanism.

[BibT_eX]

[DOI]

Nilson Maciel

Lírida A. B. Naviner

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Modeling Attack Resilient Physical Unclonable Function Based on STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Review of Sparse Recovery Algorithms.

[BibT_eX]

[DOI]

IEEE Access, 2019

Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing.

[BibT_eX]

[DOI]

Lei Xie

Jun Yang

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Deep Learning Approaches for Sparse Recovery in Compressive Sensing.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Image and Signal Processing and Analysis, 2019

Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology.

[BibT_eX]

[DOI]

Nilson Maciel

Microelectron. Reliab., 2018

A high-reliability and low-power computing-in-memory implementation within STT-MRAM.

[BibT_eX]

[DOI]

Microelectron. J., 2018

A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

MRAM-on-FDSOI Integration: A Bit-Cell Perspective.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Compressed Sensing for Wideband HF Channel Estimation.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Frontiers of Signal Processing, 2018

Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.

[BibT_eX]

[DOI]

Jacques-Olivier Klein

Microelectron. Reliab., 2016

Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

Efficient reliability evaluation methodologies for combinational circuits.

[BibT_eX]

[DOI]

Mariem Slimani

Microelectron. Reliab., 2016

A novel circuit design of true random number generator using magnetic tunnel junction.

[BibT_eX]

[DOI]

Jacques-Olivier Klein

Jianlei Yang

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Approximate computing in MOS/spintronic non-volatile full-adder.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

2015

Compact thermal modeling of spin transfer torque magnetic tunnel junction.

[BibT_eX]

[DOI]

Jacques-Olivier Klein

Microelectron. Reliab., 2015

A dual-rail compact defect-tolerant multiplexer.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2015

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2015

Cross-layer investigation of continuous-time sigma-delta modulator under aging effects.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2015

Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2015

Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2014

Reliability-aware delay faults evaluation of CMOS flip-flops.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Efficient implementation for accurate analysis of CED circuits against multiple faults.

[BibT_eX]

[DOI]

Ting An

Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Simulation study of aging in CMOS binary adders.

[BibT_eX]

[DOI]

Ting An

Proceedings of the 37th International Convention on Information and Communication Technology, 2014

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013

A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts.

[BibT_eX]

[DOI]

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology.

[BibT_eX]

[DOI]

Proceedings of Eurocon 2013, 2013

Reliability analysis of combinational circuits with the influences of noise and single-event transients.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems.

[BibT_eX]

[DOI]

J. Low Power Electron., 2012

2011

Reliability aware design of low power continuous-time sigma-delta modulator.

[BibT_eX]

[DOI]