Hanwool Jeong
Orcid: 0000-0002-7346-6739
According to our database1,
Hanwool Jeong
authored at least 33 papers
between 2012 and 2024.
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Bibliography
2024
High Efficiency Variation-Aware SRAM Timing Characterization via Machine-Learning-Assisted Netlist Extraction.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
Sensors, 2024
2023
Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
IEEE Trans. Very Large Scale Integr. Syst., May, 2023
Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
Machine Learning-Based Read Access Yield Estimation and Design Optimization for High-Density SRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
All-Digital Time-Domain Temperature Sensor for Energy Efficient On-Chip Thermal Management.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
2021
A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation.
IEEE J. Solid State Circuits, 2021
2020
IEEE Access, 2020
2019
IEEE J. Solid State Circuits, 2019
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.
IEEE J. Solid State Circuits, 2019
A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
2015
Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2012
Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM.
Proceedings of the International SoC Design Conference, 2012
Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012