Hans-Werner Lang

Affiliations:
  • Hochschule Flensburg, Germany


According to our database1, Hans-Werner Lang authored at least 13 papers between 1983 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2012
Algorithmen in Java, 3. Auflage
Oldenbourg, ISBN: 978-3-486-71406-7, 2012

2010
A Characterization of the Chomsky Hierarchy by String Turing Machines.
Proceedings of the 2010 International Conference on Foundations of Computer Science, 2010

2004
A bit-serial floating-point unit for a massively parallel system on a chip.
Parallel Algorithms Appl., 2004

2003
An Area-Efficient Bit-Serial Integer Multiplier.
Proceedings of the International Conference on VLSI, 2003

Design of a Bit-Serial Floating Point Unit for a Fine Grained Parallel Processor Array.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Algorithmen in Java
Oldenbourg, ISBN: 3-486-25900-8, 2003

1994
The Instruction Systolic Array - Implementation of a Low-Cost Parallel Architecture as Add-On Board for Personal Computers.
Proceedings of the High-Performance Computing and Networking, 1994

1989
Das befehlssystolische Prozessorfeld: Architektur und Programmierung.
PhD thesis, 1989

1988
The instruction systolic array and its relation to other models of parallel computers.
Parallel Comput., 1988

1986
The instruction systolic array - a parallel architecture for VLSI.
Integr., 1986

1985
Systolic Sorting on a Mesh-Connected Network.
IEEE Trans. Computers, 1985

A Method for Realistic Comparisons of Sorting Algorithms for VLSI.
Proceedings of the Foundations of Data Organization, 1985

1983
A Fast Sorting Algorithm for VLSI.
Proceedings of the Automata, 1983


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