Hans Vandierendonck
Orcid: 0000-0001-5868-9259
According to our database1,
Hans Vandierendonck
authored at least 117 papers
between 2000 and 2024.
Collaborative distances:
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Bibliography
2024
CoRR, 2024
The Effects of Weight Quantization on Online Federated Learning for the IoT: A Case Study.
IEEE Access, 2024
Differentiating Set Intersections in Maximal Clique Enumeration by Function and Subproblem Size.
Proceedings of the 38th ACM International Conference on Supercomputing, 2024
Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024
2023
Resource-Efficient Convolutional Networks: A Survey on Model-, Arithmetic-, and Implementation-Level Techniques.
ACM Comput. Surv., 2023
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Dataset Announcement: MS-BioGraphs, Trillion-Scale Public Real-World Sequence Similarity Graphs.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023
Proceedings of the IEEE International Conference on Big Data, 2023
2022
Increased Leverage of Transprecision Computing for Machine Vision Applications at the Edge.
J. Signal Process. Syst., 2022
IEEE Trans. Neural Networks Learn. Syst., 2022
Proceedings of the PPoPP '22: 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Seoul, Republic of Korea, April 2, 2022
Comparison of Two Microcontroller Boards for On-Device Model Training in a Keyword Spotting Task.
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022
Software-defined floating-point number formats and their application to graph processing.
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022
Proceedings of the IEEE International Conference on Data Mining, 2022
Proceedings of the Approximate Computing, 2022
2021
IEEE Trans. Signal Process., 2021
Revealing DRAM Operating GuardBands Through Workload-Aware Error Predictive Modeling.
IEEE Trans. Computers, 2021
Resource-Efficient Deep Learning: A Survey on Model-, Arithmetic-, and Implementation-Level Techniques.
CoRR, 2021
Concurr. Comput. Pract. Exp., 2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021
Proceedings of the IEEE International Symposium on Workload Characterization, 2021
Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021
Proceedings of the 5th IEEE International Conference on Fog and Edge Computing, 2021
Proceedings of the HPDC '21: The 30th International Symposium on High-Performance Parallel and Distributed Computing, 2021
Proceedings of the IEEE International Conference on Cluster Computing, 2021
Proceedings of the Workshop on Scientific Document Understanding co-located with 35th AAAI Conference on Artificial Inteligence, 2021
2020
Parallel Comput., 2020
Fast load balance parallel graph analytics with an automatic graph data structure selection algorithm.
Future Gener. Comput. Syst., 2020
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020
2019
ACM Trans. Parallel Comput., 2019
IEEE Trans. Computers, 2019
VEBO: a vertex- and edge-balanced ordering heuristic to load balance parallel graph processing.
Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2019
SAFIRE: Scalable and Accurate Fault Injection for Parallel Multithreaded Applications.
Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019
Proceedings of the IEEE International Symposium on Workload Characterization, 2019
Stream-Based Representation and Incremental optimization of Technical Market Indicators.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019
2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018
Code and Data Transformations to Address Garbage Collector Performance in Big Data Processing.
Proceedings of the 25th IEEE International Conference on High Performance Computing, 2018
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
ACM Trans. Archit. Code Optim., 2017
Proceedings of the International Conference on Supercomputing, 2017
Proceedings of the 46th International Conference on Parallel Processing, 2017
2016
Exploiting Significance of Computations for Energy-Constrained Approximate Computing.
Int. J. Parallel Program., 2016
Proceedings of the 28th ACM Symposium on Parallelism in Algorithms and Architectures, 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the Workshops of the EDBT/ICDT 2016 Joint Conference, 2016
Proceedings of the 2016 IEEE International Conference on Big Data (IEEE BigData 2016), 2016
Proceedings of the 2016 IEEE International Conference on Big Data (IEEE BigData 2016), 2016
2015
Comput. Sci. Res. Dev., 2015
IEEE Comput. Archit. Lett., 2015
A programming model and runtime system for significance-aware energy-efficient computing.
Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2015
Proceedings of the OpenMP: Heterogenous Execution and Data Movements, 2015
Proceedings of the 11th International Workshop on Data Management on New Hardware, 2015
A significance-driven programming framework for energy-constrained approximate computing.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015
2014
Fast Dynamic Binary Rewriting for flexible thread migration on shared-ISA heterogeneous MPSoCs.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Rigorous specification and low-latency implementation of technical market indicators.
Proceedings of the first workshop on Parallel programming for analytics applications, 2014
2013
ACM Trans. Archit. Code Optim., 2013
Proceedings of the International Conference for High Performance Computing, 2013
Proceedings of the Advanced Parallel Processing Technologies, 2013
2012
BDDT: : block-level dynamic dependence analysis for deterministic task-based parallelism.
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012
2011
ACM Trans. Archit. Code Optim., 2011
Proceedings of the 2011 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '11, 2011
Parallel Programming of General-Purpose Programs Using Task-Based Programming Models.
Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
Parallel Comput., 2010
Comput. J., 2010
Proceedings of the 28th International Conference on Computer Design, 2010
A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
Trans. High Perform. Embed. Archit. Compil., 2009
Proceedings of the 6th Conference on Computing Frontiers, 2009
2008
ACM Trans. Archit. Code Optim., 2008
J. Inf. Sci. Eng., 2008
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Proceedings of the Architecture of Computing Systems, 2008
2007
SIGARCH Comput. Archit. News, 2007
Proceedings of the 4th Conference on Computing Frontiers, 2007
2006
Proceedings of the 14th International Symposium on Modeling, 2006
Proceedings of the 14th International Symposium on Modeling, 2006
The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
2FAR: A 2bcgskew Predictor Fused by an Alloyed Redundant History Skewed Perceptron Branch Predictor.
J. Instr. Level Parallelism, 2005
2004
Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004
2003
J. Syst. Archit., 2003
J. Instr. Level Parallelism, 2003
Trade-offs for Skewed-Associative Caches.
Proceedings of the Parallel Computing: Software Technology, 2003
Proceedings of the 2003 Conference on Languages, 2003
2002
IEEE Comput. Archit. Lett., 2002
Proceedings of the Euro-Par 2002, 2002
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002
2001
Efficient profile-based evaluation of randomising set index functions for cache memories.
Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001
Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001
2000
Proceedings of the High Performance Computing, Third International Symposium, 2000
A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000