Hans Vandierendonck

Orcid: 0000-0001-5868-9259

According to our database1, Hans Vandierendonck authored at least 120 papers between 2000 and 2024.

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Bibliography

2024
Defending against Model Inversion Attacks via Random Erasing.
CoRR, 2024

HiRED: Attention-Guided Token Dropping for Efficient Inference of High-Resolution Vision-Language Models in Resource-Constrained Environments.
CoRR, 2024

Selective Parallel Loading of Large-Scale Compressed Graphs with ParaGrapher.
CoRR, 2024

The Effects of Weight Quantization on Online Federated Learning for the IoT: A Case Study.
IEEE Access, 2024

Differentiating Set Intersections in Maximal Clique Enumeration by Function and Subproblem Size.
Proceedings of the 38th ACM International Conference on Supercomputing, 2024

QClique: Optimizing Performance and Accuracy in Maximum Weighted Clique.
Proceedings of the Euro-Par 2024: Parallel Processing, 2024

Exploiting Data Redundancy in CKKS Encoding for High-Speed Homomorphic Encryption.
Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024

2023
Resource-Efficient Convolutional Networks: A Survey on Model-, Arithmetic-, and Implementation-Level Techniques.
ACM Comput. Surv., 2023

MS-BioGraphs: Sequence Similarity Graph Datasets.
CoRR, 2023

ROMA: Run-Time Object Detection To Maximize Real-Time Accuracy.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023

Decentralised Biomedical Signal Classification using Early Exits.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Dataset Announcement: MS-BioGraphs, Trillion-Scale Public Real-World Sequence Similarity Graphs.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

On Overcoming HPC Challenges of Trillion-Scale Real-World Graph Datasets.
Proceedings of the IEEE International Conference on Big Data, 2023

2022
Increased Leverage of Transprecision Computing for Machine Vision Applications at the Edge.
J. Signal Process. Syst., 2022

Mixed-Precision Kernel Recursive Least Squares.
IEEE Trans. Neural Networks Learn. Syst., 2022

Model-Agnostic Counterfactual Explanations in Credit Scoring.
IEEE Access, 2022

LOTUS: locality optimizing triangle counting.
Proceedings of the PPoPP '22: 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Seoul, Republic of Korea, April 2, 2022

Comparison of Two Microcontroller Boards for On-Device Model Training in a Keyword Spotting Task.
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022

SAPCo Sort: optimizing Degree-Ordering for Power-Law Graphs.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Software-defined floating-point number formats and their application to graph processing.
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

MASTIFF: structure-aware minimum spanning tree/forest.
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

Dengue Fever: From Extreme Climates to Outbreak Prediction.
Proceedings of the IEEE International Conference on Data Mining, 2022

Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific.
Proceedings of the Approximate Computing, 2022

2021
Towards Lower Precision Adaptive Filters: Facts From Backward Error Analysis of RLS.
IEEE Trans. Signal Process., 2021

Revealing DRAM Operating GuardBands Through Workload-Aware Error Predictive Modeling.
IEEE Trans. Computers, 2021

Resource-Efficient Deep Learning: A Survey on Model-, Arithmetic-, and Implementation-Level Techniques.
CoRR, 2021

Reducing the burden of parallel loop schedulers for many-core processors.
Concurr. Comput. Pract. Exp., 2021

Leveraging Transprecision Computing for Machine Vision Applications at the Edge.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

How Do Graph Relabeling Algorithms Improve Memory Locality?
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Locality Analysis of Graph Reordering Algorithms.
Proceedings of the IEEE International Symposium on Workload Characterization, 2021

Exploiting in-Hub Temporal Locality in SpMV-based Graph Processing.
Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021

TOD: Transprecise Object Detection to Maximise Real-Time Accuracy on the Edge.
Proceedings of the 5th IEEE International Conference on Fog and Edge Computing, 2021

Achieving Scalable Consensus by Being Less Writey.
Proceedings of the HPDC '21: The 30th International Symposium on High-Performance Parallel and Distributed Computing, 2021

Thrifty Label Propagation: Fast Connected Components for Skewed-Degree Graphs.
Proceedings of the IEEE International Conference on Cluster Computing, 2021

Understood in Translation: Transformers for Domain Understanding.
Proceedings of the Workshop on Scientific Document Understanding co-located with 35th AAAI Conference on Artificial Inteligence, 2021

2020
AIR: Iterative refinement acceleration using arbitrary dynamic precision.
Parallel Comput., 2020

Fast load balance parallel graph analytics with an automatic graph data structure selection algorithm.
Future Gener. Comput. Syst., 2020

Graptor: efficient pull and push style vectorized graph processing.
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

Half-Precision Floating-Point Formats for PageRank: Opportunities and Challenges.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2019
Hyperqueues: Design and Implementation of Deterministic Concurrent Queues.
ACM Trans. Parallel Comput., 2019

Fast and Energy-Efficient OLAP Data Management on Hybrid Main Memory Systems.
IEEE Trans. Computers, 2019

VEBO: a vertex- and edge-balanced ordering heuristic to load balance parallel graph processing.
Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2019

SAFIRE: Scalable and Accurate Fault Injection for Parallel Multithreaded Applications.
Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019

Workload-Aware DRAM Error Prediction using Machine Learning.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

Stream-Based Representation and Incremental optimization of Technical Market Indicators.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

2018
Int. J. High Perform. Comput. Appl., 2018

Energy-Efficient Iterative Refinement Using Dynamic Precision.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

The VINEYARD integrated framework for hardware accelerators in the cloud.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Userspace Hypervisor Data Characterization in Virtualized Environment.
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018

Code and Data Transformations to Address Garbage Collector Performance in Big Data Processing.
Proceedings of the 25th IEEE International Conference on High Performance Computing, 2018


2017
SCALO: Scalability-Aware Parallelism Orchestration for Multi-Threaded Workloads.
ACM Trans. Archit. Code Optim., 2017

GraphGrind: addressing load imbalance of graph partitioning.
Proceedings of the International Conference on Supercomputing, 2017

Accelerating Graph Analytics by Utilising the Memory Locality of Graph Partitioning.
Proceedings of the 46th International Conference on Parallel Processing, 2017

2016
Exploiting Significance of Computations for Energy-Constrained Approximate Computing.
Int. J. Parallel Program., 2016

Energy Optimization of Memory Intensive Parallel workloads.
CoRR, 2016

Brief Announcement: Energy Optimization of Memory Intensive Parallel Workloads.
Proceedings of the 28th ACM Symposium on Parallelism in Algorithms and Architectures, 2016


Operator and Workflow Optimization for High-Performance Analytics.
Proceedings of the Workshops of the EDBT/ICDT 2016 Joint Conference, 2016

HPTA: High-performance text analytics.
Proceedings of the 2016 IEEE International Conference on Big Data (IEEE BigData 2016), 2016

A scalable and composable map-reduce system.
Proceedings of the 2016 IEEE International Conference on Big Data (IEEE BigData 2016), 2016

2015
On the potential of significance-driven execution for energy-aware HPC.
Comput. Sci. Res. Dev., 2015

On the Energy-Efficiency of Byte-Addressable Non-Volatile Memory.
IEEE Comput. Archit. Lett., 2015

A programming model and runtime system for significance-aware energy-efficient computing.
Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2015

A Case Study of OpenMP Applied to Map/Reduce-Style Computations.
Proceedings of the OpenMP: Heterogenous Execution and Data Movements, 2015

Energy-Efficient In-Memory Data Stores on Hybrid Memory Hierarchies.
Proceedings of the 11th International Workshop on Data Management on New Hardware, 2015

A significance-driven programming framework for energy-constrained approximate computing.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Software-managed energy-efficient hybrid DRAM/NVM main memory.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Energy-Efficient Hybrid DRAM/NVM Main Memory.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
Energy Efficiency through Significance-Based Computing.
Computer, 2014

Fast Dynamic Binary Rewriting for flexible thread migration on shared-ISA heterogeneous MPSoCs.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Rigorous specification and low-latency implementation of technical market indicators.
Proceedings of the first workshop on Parallel programming for analytics applications, 2014

2013
Analysis of dependence tracking algorithms for task dataflow execution.
ACM Trans. Archit. Code Optim., 2013

Deterministic scale-free pipeline parallelism with hyperqueues.
Proceedings of the International Conference for High Performance Computing, 2013

BDDT: Block-Level Dynamic Dependence Analysis for Task-Based Parallelism.
Proceedings of the Advanced Parallel Processing Technologies, 2013

2012
Techniques and Tools for Parallelizing Software.
IEEE Softw., 2012

BDDT: : block-level dynamic dependence analysis for deterministic task-based parallelism.
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012

2011
Managing SMT resource usage through speculative instruction window weighting.
ACM Trans. Archit. Code Optim., 2011

Averting the Next Software Crisis.
Computer, 2011

Fairness Metrics for Multi-Threaded Processors.
IEEE Comput. Archit. Lett., 2011

A programming model for deterministic task parallelism.
Proceedings of the 2011 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '11, 2011

Parallel Programming of General-Purpose Programs Using Task-Based Programming Models.
Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism, 2011

A Unified Scheduler for Recursive and Task Dataflow Parallelism.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
A profile-based tool for finding pipeline parallelism in sequential programs.
Parallel Comput., 2010

Accelerating Multiple Sequence Alignment with the Cell BE Processor.
Comput. J., 2010

Implicit hints: Embedding hint bits in programs without ISA changes.
Proceedings of the 28th International Conference on Computer Design, 2010

A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

The Paralax infrastructure: automatic parallelization with a helping hand.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Fetch Gating Control through Speculative Instruction Window Weighting.
Trans. High Perform. Embed. Archit. Compil., 2009

Towards automatic program partitioning.
Proceedings of the 6th Conference on Computing Frontiers, 2009

2008
Speculative return address stack management revisited.
ACM Trans. Archit. Code Optim., 2008

Behavior-Based Branch Prediction by Dynamically Clustering Branch Instructions.
J. Inf. Sci. Eng., 2008

Extracting coarse-grain parallelism in general-purpose programs.
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

Experiences with Parallelizing a Bio-informatics Program on the Cell BE.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Constructing Optimal XOR-Functions to Minimize Cache Conflict Misses.
Proceedings of the Architecture of Computing Systems, 2008

2007
Function level parallelism driven by data dependencies.
SIGARCH Comput. Archit. News, 2007

Clustered indexing for branch predictors.
Microprocess. Microsystems, 2007

By-passing the out-of-order execution pipeline to increase energy-efficiency.
Proceedings of the 4th Conference on Computing Frontiers, 2007

2006
Building and Validating a Reduced TPC-H Benchmark.
Proceedings of the 14th International Symposium on Modeling, 2006

On the Impact of OS and Linker Effects on Level-2 Cache Performance.
Proceedings of the 14th International Symposium on Modeling, 2006

The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006

Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
XOR-Based Hash Functions.
IEEE Trans. Computers, 2005

2FAR: A 2bcgskew Predictor Fused by an Alloyed Redundant History Skewed Perceptron Branch Predictor.
J. Instr. Level Parallelism, 2005

Reducing TPC-H Benchmarking Time.
Proceedings of the Advances in Informatics, 2005

2004
On Generating Set Index Functions for Randomized Caches.
Comput. J., 2004

Eccentric and fragile benchmarks.
Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004

2003
Highly accurate and efficient evaluation of randomising set index functions.
J. Syst. Archit., 2003

Quantifying the Impact of Input Data Sets on Program Behavior and its Applications.
J. Instr. Level Parallelism, 2003

Designing Computer Architecture Research Workloads.
Computer, 2003

Trade-offs for Skewed-Associative Caches.
Proceedings of the Parallel Computing: Software Technology, 2003

On the side-effects of code abstraction.
Proceedings of the 2003 Conference on Languages, 2003

Trace Substitution.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002
An Address Transformation Combining Block- and Word-Interleaving.
IEEE Comput. Archit. Lett., 2002

A Comparative Study of Redundancy in Trace Caches (Research Note).
Proceedings of the Euro-Par 2002, 2002

Workload Design: Selecting Representative Program-Input Pairs.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
Efficient profile-based evaluation of randomising set index functions for cache memories.
Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001

Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000
A Comparison of Locality-Based and Recency-Based Replacement Policies.
Proceedings of the High Performance Computing, Third International Symposium, 2000

A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000


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