Hans Reyserhove
Orcid: 0000-0002-5368-3533
According to our database1,
Hans Reyserhove
authored at least 6 papers
between 2014 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
Proceedings of the IEEE Conference on Virtual Reality and 3D User Interfaces, 2022
2018
Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS.
IEEE J. Solid State Circuits, 2018
2017
A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs.
IEEE J. Solid State Circuits, 2017
Design margin elimination in a near-threshold timing error masking-aware 32-bit ARM Cortex M0 in 40nm CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
A 16.07pJ/cycle 31MHz fully differential transmission gate logic ARM Cortex M0 core in 40nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014