Hans-Joachim Wunderlich

Hongyan Zhang

Jörg Henkel

Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011

Variation-aware fault modeling.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2011

Efficient multi-level fault simulation of HW/SW systems for structural faults.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2011

P-PET: Partial pseudo-exhaustive test for high defect coverage.

[BibT_eX]

[DOI]

Abdullah Mumtaz

Proceedings of the 2011 IEEE International Test Conference, 2011

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Soft error correction in embedded storage elements.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Fail-safety in core-based system design.

[BibT_eX]

[DOI]

Rafal Baranowski

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Towards Variation-Aware Test Methods.

[BibT_eX]

[DOI]

Ilia Polian

Bernd Becker

Peter C. Maxwell

Proceedings of the 16th European Test Symposium, 2011

Structural Test for Graceful Degradation of NoC Switches.

[BibT_eX]

[DOI]

Atefe Dalirsani

Proceedings of the 16th European Test Symposium, 2011

Structural In-Field Diagnosis for Random Logic Circuits.

[BibT_eX]

[DOI]

Alejandro Cook

Ulrich Abelein

Proceedings of the 16th European Test Symposium, 2011

SAT-based fault coverage evaluation in the presence of unknown values.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Design and architectures for dependable embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Embedded Test for Highly Accurate Defect Localization.

[BibT_eX]

[DOI]

Abdullah Mumtaz

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Efficient BDD-based Fault Simulation in Presence of Unknown Values.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Diagnostic Test of Robust Circuits.

[BibT_eX]

[DOI]

Alejandro Cook

Thomas Indlekofer

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen (Algorithm-based Fault-Tolerance on Many-Core Architectures).

[BibT_eX]

[DOI]

Claus Braun

it Inf. Technol., 2010

Efficient Concurrent Self-Test with Partially Specified Patterns.

[BibT_eX]

[DOI]

J. Electron. Test., 2010

Low-power test planning for arbitrary at-speed delay-test clock schemes.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Parity prediction synthesis for nano-electronic gate designs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

System reliability evaluation using concurrent multi-level simulation of structural faults.

[BibT_eX]

[DOI]

Nadereh Hatami

Proceedings of the 2011 IEEE International Test Conference, 2010

Algorithm-based fault tolerance for many-core architectures.

[BibT_eX]

[DOI]

Claus Braun

Proceedings of the 15th European Test Symposium, 2010

Massive statistical process variations: A grand challenge for testing nanoelectronic circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

BISD: Scan-based Built-In self-diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Efficient fault simulation on many-core processors.

[BibT_eX]

[DOI]

Marcel Schaal

Proceedings of the 47th Design Automation Conference, 2010

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level.

[BibT_eX]

[DOI]

Nadereh Hatami

Proceedings of the 19th IEEE Asian Test Symposium, 2010

On Determining the Real Output Xs by SAT-Based Reasoning.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Adaptive Debug and Diagnosis Without Fault Dictionaries.

[BibT_eX]

[DOI]

J. Electron. Test., 2009

Restrict Encoding for Mixed-Mode BIST.

[BibT_eX]

[DOI]

Abdul Wahid Hakmi

Friedrich Hapke

Andreas Glowatz

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE European Test Symposium, 2009

Test Encoding for Extreme Response Compaction.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE European Test Symposium, 2009

Software-Based Hardware Fault Tolerance for Many-Core Architectures.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Test exploration and validation using transaction level models.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

A diagnosis algorithm for extreme space compaction.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Signature Rollback - A Technique for Testing Robust Circuits.

[BibT_eX]

[DOI]

Uranmandakh Amgalan

Christian Hachmann

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Integrating Scan Design and Soft Error Correction in Low-Power Applications.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Selective Hardening in Early Design Steps.

[BibT_eX]

[DOI]

Ilia Polian

Bernd Becker

Proceedings of the 13th European Test Symposium, 2008

Test Set Stripping Limiting the Maximum Number of Specified Bits.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Scan Chain Organization for Embedded Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Scan chain clustering for test power reduction.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Deterministic logic BIST for transition fault testing.

[BibT_eX]

[DOI]

Michael Garbers

IET Comput. Digit. Tech., 2007

Programmable deterministic Built-In Self-Test.

[BibT_eX]

[DOI]

Abdul Wahid Hakmi

Proceedings of the 2007 IEEE International Test Conference, 2007

Synthesis of irregular combinational functions with large don't care sets.

[BibT_eX]

[DOI]

R. D. Mascarenhas

Michael Garbers

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.

[BibT_eX]

[DOI]

Philipp Öhler

Proceedings of the 12th European Test Symposium, 2007

A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.

[BibT_eX]

[DOI]

Stefan Ludwig

Torsten Coym

Bernd Straube

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.

[BibT_eX]

[DOI]

Philipp Öhler

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Scan Test Planning for Power Reduction.

[BibT_eX]

[DOI]

Nicolas Mäding

Jens Leenstra

Proceedings of the 44th Design Automation Conference, 2007

2006

X-masking during logic BIST and its impact on defect coverage.

[BibT_eX]

[DOI]

Yuyi Tang

IEEE Trans. Very Large Scale Integr. Syst., 2006

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).

[BibT_eX]

[DOI]

it Inf. Technol., 2006

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.

[BibT_eX]

[DOI]

Nabil Badereddine

Patrick Girard

Christian Landrault

Arnaud Virazel

Proceedings of the IFIP VLSI-SoC 2006, 2006

BIST Power Reduction Using Scan-Chain Disable in the Cell Processor.

[BibT_eX]

[DOI]

Nicolas Mäding

Jens Leenstra

Proceedings of the 2006 IEEE International Test Conference, 2006

Some Common Aspects of Design Validation, Debug and Diagnosis.

[BibT_eX]

[DOI]

Talal Arnaout

Gunter Bartsch

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Software-based self-test of processors under power constraints.

[BibT_eX]

[DOI]

Jun Zhou

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Implementing a Scheme for External Deterministic Self-Test.

[BibT_eX]

[DOI]

Abdul Wahid Hakmi

Michael Garbers

Luis Leonardo Azuara-Gomez

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Development of an audio player as system-on-a-chip using an open source platform.

[BibT_eX]

[DOI]

Pattara Kiatisevi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung.

[BibT_eX]

[DOI]

Jun Zhou

Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

On the Reliability Evaluation of SRAM-Based FPGA Designs.

[BibT_eX]

[DOI]

Olivier Héron

Talal Arnaout

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

From embedded test to embedded diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

2004

Panel Summaries.

[BibT_eX]

Sandeep K. Shukla

IEEE Des. Test Comput., 2004

X-Masking During Logic BIST and Its Impact on Defect Coverage.

[BibT_eX]

[DOI]

Yuyi Tang

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Efficient Pattern Mapping for Deterministic Logic BIST.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Impact of Test Point Insertion on Silicon Area and Timing during Layout.

[BibT_eX]

[DOI]

Ferry Syafei Sapei

Proceedings of the 2004 Design, 2004

Reliability Considerations forMechatronic Systems on the Basis of a State Model.

[BibT_eX]

[DOI]

Talal Arnaout

Peter Göhner

Eduard Zimmer

Proceedings of the ARCS 2004, 2004

2003

Introduction.

[BibT_eX]

[DOI]

Shishpal Rawat

ACM Trans. Design Autom. Electr. Syst., 2003

Test Engineering Education in Europe: the EuNICE-Test Project.

[BibT_eX]

[DOI]

Jean-Pierre Van der Heyden

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

2002

Efficient Online and Offline Testing of Embedded DRAMs.

[BibT_eX]

[DOI]

Alexander A. Ivaniuk

Yuri V. Klimets

IEEE Trans. Computers, 2002

A Mixed-Mode BIST Scheme Based on Folding Compression.

[BibT_eX]

[DOI]

Huaguo Liang

J. Comput. Sci. Technol., 2002

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.

[BibT_eX]

[DOI]

Huaguo Liang

J. Electron. Test., 2002

Reusing Scan Chains for Test Pattern Decompression.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

High Defect Coverage with Low-Power Test Sequences in a BIST Environment.

[BibT_eX]

[DOI]

Patrick Girard

Christian Landrault

Arnaud Virazel

IEEE Des. Test Comput., 2002

Adapting an SoC to ATE Concurrent Test Capabilities.

[BibT_eX]

[DOI]

Ramón Huerta Rivera

Martin Fischer

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Combining deterministic logic BIST with test point insertion.

[BibT_eX]

[DOI]

Florian Meister

Proceedings of the 7th European Test Workshop, 2002

RESPIN++ - deterministic embedded test.

[BibT_eX]

[DOI]

Lars Schäfer

Proceedings of the 7th European Test Workshop, 2002

2001

Application of Deterministic Logic BIST on Industrial Circuits.

[BibT_eX]

[DOI]

Erik Jan Marinissen

J. Electron. Test., 2001

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.

[BibT_eX]

[DOI]

Huaguo Liang

J. Electron. Test., 2001

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.

[BibT_eX]

[DOI]

Patrick Girard

Loïs Guiller

Christian Landrault

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Tailoring ATPG for embedded testing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Circuit partitioning for efficient logic BIST synthesis.

[BibT_eX]

[DOI]

Alexander Irion

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Using mission logic for embedded testing.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

On applying the set covering model to reseeding.

[BibT_eX]

[DOI]

Silvia Chiusano

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Deterministic BIST with Partial Scan.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Minimized Power Consumption for Scan-Based BIST.

[BibT_eX]

[DOI]

Stefan Gerstendörfer

J. Electron. Test., 2000

Non-intrusive BIST for systems-on-a-chip.

[BibT_eX]

[DOI]

Silvia Chiusano

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Optimal Hardware Pattern Generation for Functional BIST.

[BibT_eX]

[DOI]

Silvia Cataldo

Silvia Chiusano

Proceedings of the 2000 Design, 2000

1999

Deterministic BIST with Multiple Scan Chains.

[BibT_eX]

[DOI]

J. Electron. Test., 1999

Error Detecting Refreshment for Embedded DRAMs.

[BibT_eX]

[DOI]

Alexander A. Ivaniuk

Yuri V. Klimets

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.

[BibT_eX]

[DOI]

I. V. Bykov

Proceedings of the Dependable Computing, 1999

Symmetric Transparent BIST for RAMs.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

Hardware-optimal test register insertion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

BIST for systems-on-a-chip.

[BibT_eX]

[DOI]

Integr., 1998

Mixed-Mode BIST Using Embedded Processors.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

Synthesizing Fast, Online-Testable Control Units.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1998

Fast Self-Recovering Controllers.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Accumulator based deterministic BIST.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST.

[BibT_eX]

[DOI]

Madhavi Karkala

Nur A. Touba

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Guest Editorial.

[BibT_eX]

[DOI]

Kwang-Ting Cheng

Kewal K. Saluja

J. Electron. Test., 1997

Power Dissipation During Testing: Should We Worry About it?

[BibT_eX]

[DOI]

Yervant Zorian

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Using BIST Control for Pattern Generation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Fast controllers for data dominated applications.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

1996

Bit-flipping BIST.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Deterministic Pattern Generation for Weighted Random Pattern Testing.

[BibT_eX]

[DOI]

Birgit Reeb

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Test register insertion with minimum hardware cost.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Pattern generation for a deterministic BIST scheme.

[BibT_eX]

[DOI]

Birgit Reeb

Steffen Tarnick

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Synthesis of I<sub>DDQ</sub>-testable circuits: integrating built-in current sensors.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Configuring Flip-Flops to BIST Registers.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Simulation Results of an Efficient Defect-Analysis Procedure.

[BibT_eX]

[DOI]

Olaf Stern

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

An efficient procedure for the synthesis of fast self-testable controller structures.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Synthesis of Self-Testable Controllers.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1992

The pseudoexhaustive test of sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Optimized synthesis techniques for testable sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Prüfgerechter Entwurf und Test hochintegrierter Schaltungen.

[BibT_eX]

Michael H. Schulz

Inform. Spektrum, 1992

1991

A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic.

[BibT_eX]

[DOI]

Thomas Kropf

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Emulation of Scan Paths in Sequential Circuit Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

Signature Analysis and Test Scheduling for Self-Testable Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

A Unified Approach for the Synthesis of Self-Testable Finite State Machines.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

1990

Multiple distributions for biased random test patterns.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

An analytical approach to the partial scan problem.

[BibT_eX]

[DOI]

Arno Kunzmann

J. Electron. Test., 1990

Error masking in self-testable circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Generating pseudo-exhaustive vectors for external testing.

[BibT_eX]

[DOI]

Oliver F. Haberl

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Optimized synthesis of self-testable finite state machines.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

The effectiveness of different test sets for PLAs.

[BibT_eX]

[DOI]

Peter C. Maxwell

Proceedings of the European Design Automation Conference, 1990

Tools and devices supporting the pseudo-exhaustive test.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference, 1990

1989

The Pseudo-Exhaustive Test of Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1989, 1989

The design of random-testable sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988

Automatisierung des Entwurfs vollständig testbarer Schaltungen.

[BibT_eX]

[DOI]

Proceedings of the GI, 1988

Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits.

[BibT_eX]

[DOI]

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987

On Computing Optimized Input Probabilities for Random Tests.

[BibT_eX]

[DOI]

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

Probabilistische Verfahren für den Test hochintegrierter Schaltungen

[BibT_eX]

[DOI]

Informatik-Fachberichte 140, Springer, ISBN: 3-540-18072-9, 1987

1986

On fault modeling for dynamic MOS circuits.

[BibT_eX]

[DOI]

Wolfgang Rosenstiel

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985

PROTEST: a tool for probabilistic testability analysis.

[BibT_eX]

[DOI]