Hans Hegt

Affiliations:
  • Eindhoven University of Technology, Department of Electrical Engineering, The Netherlands


According to our database1, Hans Hegt authored at least 51 papers between 1991 and 2017.

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Bibliography

2017
Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Higher-order DWA in bandpass delta-sigma modulators and its implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A Background Calibration Technique Based on Limit Cycles for Reconfigurable Sigma Delta Modulators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Automatic filter calibration for bandpass delta-sigma modulators.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Bitstream switching rate based calibration of delta-sigma modulators.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A femto-ampere sensitive direct-interface current-input sigma delta ADC for amperometric bio-sensor signal acquisition.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Limit cycle counting based smart background calibration of continuous time sigma delta ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Sigma delta feedback DAC architectures for high accuracy and extremely low charge transfer.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals.
Proceedings of the ESSCIRC 2013, 2013

2012
An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < - 83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping.
IEEE J. Solid State Circuits, 2011

An 11b pipeline ADC with dual sampling technique for converting multi-carrier signals.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Timing error measurement for highly linear wideband Digital to Analog Converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009
Analog calibration of channel mismatches in time-interleaved ADCs.
Int. J. Circuit Theory Appl., 2009

Smart Front-Ends, from Vision to Design.
IEICE Trans. Electron., 2009

2008
Predictive timing error calibration technique for RF current-steering DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A flexible 12-bit self-calibrated quad-core current-steering DAC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption.
Integr., 2007

Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Parallel current-steering D/A Converters for Flexibility and Smartness.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Analysis of Open Loop Track-and-Hold Circuits.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Sigma-delta modulators operating at a limit cycle.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer.
IEEE J. Solid State Circuits, 2006

DDL-based calibration techniques for timing errors in current-steering DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A binary-to-thermometer decoder with built-in redundancy for improved DAC yield.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Digital post-correction of front-end track-and-hold circuits in ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Power Optimization for Pipelined ADCs with Open-Loop Residue Amplifiers.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A CMOS V-I converter with 75-dB SFDR and 360-μW power consumption.
IEEE J. Solid State Circuits, 2005

A flexible ADC approach for mixed-signal SoC platforms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Smart AD and DA converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A start-up calibration method for generic current-steering D/A converters with optimal area solution.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An on-chip self-calibration method for current mismatch in D/A converters.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
CMOS V-I converter with 75dB SFDR and 360μW power consumption.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresis.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002
A 3.3-mW ΣΔ modulator for UMTS in 0.18-μm CMOS with 70-dB dynamic range in 2-MHz bandwidth.
IEEE J. Solid State Circuits, 2002

2001
Terminal dynamics approach to cellular neural networks.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

On the stability of high order Sigma-Delta modulators.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1999
Recognition of Real-Life Character Samples using a Structural Variation and Degradation Model.
Proceedings of the Fifth International Conference on Document Analysis and Recognition, 1999

1998
On Structural Modelling for Omnifont and Handwritten Character Recognition.
Proceedings of the Advances in Pattern Recognition, 1998

A variation and distortion tolerant structural pre-classifier for hierarchical character recognition.
Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, 1998

A flexible and robust matching scheme for character recognition to cope with variations in spatial interrelation among structural features.
Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, 1998

A high performance license plate recognition system.
Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, 1998

1996
A 3.3 V 625 kHz switched-current multiplier.
IEEE J. Solid State Circuits, 1996

A low power high performance switched-current multiplier.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
A High Performance Low Voltage Switched-Current Multiplier.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1991
Finding all solutions of piecewise linear functions and application to circuit design.
Int. J. Circuit Theory Appl., 1991


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