Hanna Park
According to our database1,
Hanna Park
authored at least 5 papers
between 2011 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
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2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
IEEE J. Solid State Circuits, January, 2025
2024
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2017
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2012
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking.
IEEE J. Solid State Circuits, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011