Hang-Ting Lue

Orcid: 0000-0003-1078-1333

According to our database1, Hang-Ting Lue authored at least 16 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Charge Loss Improvement in 3D Flash Memory by Molecular Oxidation of Tunneling Oxide.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F<sup>2</sup> DRAM Below Equivalent 10nm Node.
Proceedings of the IEEE International Memory Workshop, 2024

Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection.
Proceedings of the IEEE International Memory Workshop, 2024

2023
Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device.
Proceedings of the IEEE International Memory Workshop, 2023

2022
First Experimental Study of Floating-Body Cell Transient Reliability Characteristics of Both N- and P-Channel Vertical Gate-All-Around Devices with Split-Gate Structures.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits.
Proceedings of the IEEE International Memory Workshop, 2021

Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances.
Proceedings of the IEEE International Memory Workshop, 2021

2020
Introduction of Non-Volatile Computing In Memory (nvCIM) by 3D NAND Flash for Inference Accelerator of Deep Neural Network (DNN) and the Read Disturb Reliability Evaluation : (Invited Paper).
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2015
Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations.
IEEE J. Solid State Circuits, 2015

2014
On Trading Wear-leveling with Heal-leveling.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2011
State-of-the-art flash memory devices and post-flash emerging memories.
Sci. China Inf. Sci., 2011

2002
Microwave penetration depth measurement for high T<sub>c</sub> superconductors by dielectric resonators.
IEEE Trans. Instrum. Meas., 2002


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