Hana Krichene

Orcid: 0000-0003-2599-7217

According to our database1, Hana Krichene authored at least 8 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

2012
2014
2016
2018
2020
2022
2024
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Links

On csauthors.net:

Bibliography

2024
A dataflow architecture with distributed control for DNN acceleration.
Proceedings of the 13th Mediterranean Conference on Embedded Computing, 2024

2023
AINoC: New Interconnect for Future Deep Neural Network Accelerators.
Proceedings of the Design and Architecture for Signal and Image Processing, 2023

2021
Analysis of on-chip communication properties in accelerator architectures for deep neural networks.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021

DSM: Data Sharing Management system for in-vehicle communication.
Proceedings of the IEEE Symposium on Computers and Communications, 2021

2019
SCAC: Weakly-coupled execution model for massively parallel systems.
Microprocess. Microsystems, 2019

2016
SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

2013
Master-Slave Control Structure for Massively Parallel System on Chip.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Broadcast with mask on a massively parallel processing on a chip.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012


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