Han-Gyeol Mun

According to our database, Han-Gyeol Mun authored at least 6 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste.

Seunghyun Moon, Han-Gyeol Mun, Hyunwoo Son, Jae-Yoon Sim

IEEE J. Solid State Circuits, January, 2024

2023

Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications.

Han-Gyeol Mun, Seunghyun Moon, Byungjun Kim, Kyeong-Jun Lee, Jae-Yoon Sim

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

A 28 nm 66.8 TOPS/W Sparsity-Aware Dynamic-Precision Deep-Learning Processor.

Han-Gyeol Mun, Hyunwoo Son, Seunghyun Moon, Jaehyun Park, ByungJun Kim, Jae-Yoon Sim

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 127.8TOPS/W Arbitrarily Quantized 1-to-8b Scalable-Precision Accelerator for General-Purpose Deep Learning with Reduction of Storage, Logic and Latency Waste.

Seunghyun Moon, Han-Gyeol Mun, Hyunwoo Son, Jae-Yoon Sim

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Joint Optimization of Cache Management and Graph Reordering for GCN Acceleration.

Kyeong-Jun Lee, ByungJun Kim, Han-Gyeol Mun, Seunghyun Moon, Jae-Yoon Sim

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

2022

An 8.9-71.3 TOPS/W Deep Learning Accelerator for Arbitrarily Quantized Neural Networks.

Seunghyun Moon, Kyeong-Jun Lee, Han-Gyeol Mun, Byungjun Kim, Jae-Yoon Sim

IEEE Trans. Circuits Syst. II Express Briefs, 2022