Hamzeh Ahangari

Orcid: 0000-0001-9272-816X

According to our database1, Hamzeh Ahangari authored at least 11 papers between 2015 and 2023.

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Bibliography

2023
Architecture for safety-critical transportation systems.
Microprocess. Microsystems, April, 2023

HLS-based High-throughput and Work-efficient Synthesizable Graph Processing Template Pipeline.
ACM Trans. Embed. Comput. Syst., March, 2023

2020
Custom hardware optimizations for reliable and high performance computer architectures (Güvenilir ve yüksek performanslı bilgisayar mimarileri için özel donanım optimizasyonları)
PhD thesis, 2020

Analysis of Design Parameters in Safety-Critical Computers.
IEEE Trans. Emerg. Top. Comput., 2020

Power-efficient reliable register file for aggressive-environment applications.
IET Comput. Digit. Tech., 2020

Temperature-Aware Core Mapping for Heterogeneous 3D NoC Design Through Constraint Programming.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

2018
A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance.
IEEE Embed. Syst. Lett., 2018

2017
Reconfigurable Hardened Latch and Flip-Flop for FPGAs.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Register file reliability enhancement through adjacent narrow-width exploitation.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

NS-SRAM: Neighborhood Solidarity SRAM for Reliability Enhancement of SRAM Memories.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015


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