Hamid Shojaei

According to our database1, Hamid Shojaei authored at least 17 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
"Constructing Machine Learning models for Orthodontic Treatment Planning: a comparison of different methods".
Proceedings of the IEEE International Conference on Big Data, 2022

2021
Learning Semantic Representations to Verify Hardware Designs.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

2013
Collaborative Multiobjective Global Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A fast and scalable multidimensional multiple-choice knapsack heuristic.
ACM Trans. Design Autom. Electr. Syst., 2013

Planning for local net congestion in global routing.
Proceedings of the International Symposium on Physical Design, 2013

2012
Confidentiality preserving integer programming for global routing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Congestion analysis for global routing via integer programming.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Torc: towards an open-source tool flow.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
A pareto-algebraic framework for signal power optimization in global routing.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Trace signal selection to enhance timing and logic visibility in post-silicon validation.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009
A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management.
Proceedings of the 46th Design Automation Conference, 2009

2008
SPaC: a symbolic pareto calculator.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007
A New Approach for Design and Verification of Transaction Level Models.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Optimized Assignment Coverage Computation in Formal Verification of Digital Systems.
Proceedings of the 16th Asian Test Symposium, 2007

2006
Signal Coverage Computation in Formal Verification.
Proceedings of the IFIP VLSI-SoC 2006, 2006

2005
TED+: a data structure for microprocessor verification.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Techniques for Formal Verification of Digital Systems: A System Approach.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004


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