Hamed Dorosti

According to our database, Hamed Dorosti authored at least 5 papers between 2010 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications.

Farzaneh Nakhaee, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Sied Mehdi Fakhraie, Hamed Dorosti

Integr., 2018

2016

Ultralow-Energy Variation-Aware Design: Adder Architecture Study.

Hamed Dorosti, Ali Teymouri, Sied Mehdi Fakhraie, Mostafa E. Salehi

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Process variation-aware approximation for efficient timing management of digital circuits.

Mohsen Faryabi, Hamed Dorosti, Mehdi Modarressi, Sied Mehdi Fakhraie

Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2011

Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling.

Farshad Firouzi, Amir Yazdanbakhsh, Hamed Dorosti, Sied Mehdi Fakhraie

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications.

Mostafa E. Salehi, Hamed Dorosti, Sied Mehdi Fakhraie

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010