Hajer Saidi

Orcid: 0000-0002-6408-4843

According to our database1, Hajer Saidi authored at least 6 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Development and Analysis of Novel Mesh of Tree-based embedded FPGA.
J. Supercomput., 2022

2021
Exploration of Word Width and Cluster Size Effects on Tree-Based Embedded FPGA Using an Automation Framework.
J. Circuits Syst. Comput., 2021

2020
Implementation of Reed Solomon Encoder on Low-Latency Embedded FPGA in Flexible SoC based on ARM Processor.
Proceedings of the 16th International Wireless Communications and Mobile Computing Conference, 2020

Novel Synthesizable eFPGA based on Island Network with Multilevel Switch Boxes.
Proceedings of the 17th IEEE/ACS International Conference on Computer Systems and Applications, 2020

2019
New CAD Tools to ConFigure Tree-Based Embedded FPGA.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

2016
Embedded FPGA accelerator for Wireless Sensor Network nodes.
Proceedings of the 11th International Design & Test Symposium, 2016


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