Haixia Wang

Orcid: 0009-0008-0474-5030

Affiliations:
  • Tsinghua University, Beijing National Research Center for Information Science and Technology, Beijing, China
  • Chinese Academy of Sciences, Beijing, China (PhD 2004)


According to our database1, Haixia Wang authored at least 43 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUs.
ACM Trans. Design Autom. Electr. Syst., January, 2024

SCAFinder: Formal Verification of Cache Fine-Grained Features for Side Channel Detection.
IEEE Trans. Inf. Forensics Secur., 2024

2023
Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
DynaComm: Accelerating Distributed CNN Training Between Edges and Clouds Through Dynamic Communication Scheduling.
IEEE J. Sel. Areas Commun., 2022

PMUSpill: The Counters in Performance Monitor Unit that Leak SGX-Protected Secrets.
CoRR, 2022

SSB-Tree: Making Persistent Memory B+- Trees Crash-Consistent and Concurrent by Lazy-Box.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022

Model Checking for Microarchitectural Data Sampling Security.
Proceedings of the 7th IEEE International Conference on Data Science in Cyberspace, 2022

CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security: (Invited Paper).
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2020
Parallelizing and optimizing neural Encoder-Decoder models without padding on multi-core architecture.
Future Gener. Comput. Syst., 2020

An Adaptive Erasure-Coded Storage Scheme with an Efficient Code-Switching Algorithm.
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020

CARD: A Congestion-Aware Request Dispatching Scheme for Replicated Metadata Server Cluster.
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020

CRaft: An Erasure-coding-supported Version of Raft for Reducing Storage Cost and Network Cost.
Proceedings of the 18th USENIX Conference on File and Storage Technologies, 2020

2019
Fast Recovery Techniques for Erasure-coded Clusters in Non-uniform Traffic Network.
Proceedings of the 48th International Conference on Parallel Processing, 2019

2017
Cache Friendly Parallelization of Neural Encoder-Decoder Models Without Padding on Multi-core Architecture.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Data-centric computation mode for convolution in deep neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

FEBRE: A Fast and Efficient Bit-Flipping Reduction Technique to Extend PCM lifetime.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

GDCRT: In-Memory 2D Geographical Dynamic Cascading Range Tree.
Proceedings of the Advanced Parallel Processing Technologies, 2017

2016
MAC: a novel systematically multilevel cache replacement policy for PCM memory.
CoRR, 2016

Pull-off buffer: Borrowing cache space to avoid deadlock for fault-tolerant NoC routing.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Parallelizing Convolutional Neural Networks on Intel $$^{\textregistered }$$ Many Integrated Core Architecture.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

2013
The Case of Using Multiple Streams in Streaming.
Int. J. Autom. Comput., 2013

Security Memory System for Mobile Device or Computer Against Memory Attacks.
Proceedings of the Trustworthy Computing and Services, 2013

Data Access Type Aware Replacement Policy for Cache Clustering Organization of Chip Multiprocessors.
Proceedings of the Advanced Parallel Processing Technologies, 2013

2012
Wear-Resistant Hybrid Cache Architecture with Phase Change Memory.
Proceedings of the Seventh IEEE International Conference on Networking, 2012

Dynamic reusability-based replication with network address mapping in CMPs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Proximity-Aware cache Replication.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction.
IEICE Trans. Electron., 2011

Coherent Temporal Streams in PARSEC.
Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

High performance cache block replication using re-reference probability in CMPs.
Proceedings of the 18th International Conference on High Performance Computing, 2011

A Read-Write Aware Replacement Policy for Phase Change Memory.
Proceedings of the Advanced Parallel Processing Technologies - 9th International Symposium, 2011

Enhanced Adaptive Insertion Policy for Shared Caches.
Proceedings of the Advanced Parallel Processing Technologies - 9th International Symposium, 2011

Scalable Proximity-Aware Cache Replication in Chip Multiprocessors.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors.
J. Comput. Sci. Technol., 2010

Hierarchical Cache Directory for CMP.
J. Comput. Sci. Technol., 2010

A Cache Replacement Policy Using Adaptive Insertion and Re-reference Prediction.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

Fast Hierarchical Cache Directory: A Scalable Cache Organization for Large-Scale CMP.
Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010

2009
Network caching for Chip Multiprocessors.
Proceedings of the 28th International Performance Computing and Communications Conference, 2009

A Novel Cache Organization for Tiled Chip Multiprocessor.
Proceedings of the Advanced Parallel Processing Technologies, 8th International Symposium, 2009

An Efficient Lightweight Shared Cache Design for Chip Multiprocessors.
Proceedings of the Advanced Parallel Processing Technologies, 8th International Symposium, 2009

2007
Exploit Temporal Locality of Shared Data in SRC Enabled CMP.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2007

LIRAC: Using Live Range Information to Optimize Memory Access.
Proceedings of the Architecture of Computing Systems, 2007

2006
SRC-based Cache Coherence Protocol in Chip Multiprocessor.
Proceedings of the Japan-China Joint Workshop on Frontier of Computer Science and Technology, 2006

Acceleration Techniques for Chip-Multiprocessor Simulator Debug.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006


  Loading...