Haitham Akkary

According to our database1, Haitham Akkary authored at least 47 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2020
Optimized Distribution of an Accelerated Convolutional Neural Network across Multiple FPGAs.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
FeatherNet: An Accelerated Convolutional Neural Network Design for Resource-constrained FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2019

Speedy Cloud: Cloud Computing with Support for Hardware Acceleration Services.
IEEE Trans. Cloud Comput., 2019

2018
Towards distributed acceleration of image processing applications using reconfigurable active SSD clusters: a case study of seismic data analysis.
Int. J. High Perform. Comput. Netw., 2018

Optimal Task Scheduling for Distributed Cluster With Active Storage Devices and Accelerated Nodes.
IEEE Access, 2018

RESTful Hardware Microservices Using Reconfigurable Networked Accelerators in Cloud and Edge Datacenters.
Proceedings of the 7th IEEE International Conference on Cloud Networking, 2018

2017
Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016
On the effectiveness of accelerating MapReduce functions using the Xilinx Vivado HLS tool.
Int. J. High Perform. Syst. Archit., 2016

FPGA-Based Accelerator for Deep Convolutional Neural Networks for the SPARK Environment.
Proceedings of the 2016 IEEE International Conference on Smart Cloud, 2016

Middleware Support for Seamless Integration of Domain Specific Cores in Cloud Datacenters.
Proceedings of the 2016 IEEE International Conference on Smart Cloud, 2016

2015
A small and power efficient checkpoint core architecture for manycore processors.
Int. J. High Perform. Syst. Archit., 2015

Issues in Trustworthy Software Systems.
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

Voice Verification System for Mobile Devices based on ALIZE/LIA_RAL.
Proceedings of the ICPRAM 2015, 2015

FPGA-Accelerated Hadoop Cluster for Deep Learning Computations.
Proceedings of the IEEE International Conference on Data Mining Workshop, 2015

2014
Hadoop Extensions for Distributed Computing on Reconfigurable Active SSD Clusters.
ACM Trans. Archit. Code Optim., 2014

Tuning the continual flow pipeline architecture with virtual register renaming.
ACM Trans. Archit. Code Optim., 2014

On the efficiency of automatically generated accelerators for reconfigurable active SSDs.
Proceedings of the 26th International Conference on Microelectronics, 2014

2013
Tuning the continual flow pipeline architecture.
Proceedings of the International Conference on Supercomputing, 2013

RASSD: A dynamically reconfigurable active storage device for energy efficient data analytics.
Proceedings of the 4th Annual International Conference on Energy Aware Computing Systems and Applications, 2013

A Mediation Layer for Connecting Data-Intensive Applications to Reconfigurable Data Nodes.
Proceedings of the 22nd International Conference on Computer Communication and Networks, 2013

Virtual register renaming: energy efficient substrate for continual flow pipelines.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Streamlining the continual flow processor architecture with fast replay loop.
Proceedings of Eurocon 2013, 2013

Virtual Register Renaming.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012
Disjoint out-of-order execution processor.
ACM Trans. Archit. Code Optim., 2012

Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value Prediction.
ACM Trans. Archit. Code Optim., 2012

An operating system for a Reconfigurable Active SSD processing node.
Proceedings of the 19th International Conference on Telecommunications, 2012

Thermal status and workload prediction using support vector regression.
Proceedings of the International Conference on Energy Aware Computing, 2012

2011
X86-ARM binary hardware interpreter.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Multiple instruction sets architecture (MISA).
Proceedings of the International Conference on Energy Aware Computing, 2011

Simultaneous continual flow pipeline architecture.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A Distributed Reconfigurable Active SSD Platform for Data Intensive Applications.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

2010
The potential of using dynamic information flow analysis in data value prediction.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2008
On the potential of latency tolerant execution in speculative multithreading.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008

A simple latency tolerant processor.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Transparent control independence (TCI).
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Scalable Load and Store Processing in Latency-Tolerant Processors.
IEEE Micro, 2006

2004
An analysis of a resource efficient checkpoint architecture.
ACM Trans. Archit. Code Optim., 2004

Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance.
IEEE Micro, 2004

A Minimal Dual-Core Speculative Multi-Threading Architecture.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Reducing Branch Misprediction Penalty via Selective Branch Recovery.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Perceptron-Based Branch Confidence Estimation.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Continual flow pipelines.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2003
Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers.
IEEE Micro, 2003

Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Recycling waste: exploiting wrong-path execution to improve branch prediction.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

2000
The Case for Speculative Multithreading on SMT Processors.
Proceedings of the High Performance Computing, Third International Symposium, 2000

1998
A Dynamic Multithreading Processor.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998


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