Haibo Wang

Affiliations:
  • Southern Illinois University, Carbondale, IL, USA


According to our database1, Haibo Wang authored at least 46 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
High Precision Winner-Take-All Circuit for Neural Networks.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Constraints-Aware Training (CAT) to Enable Software-Hardware Co-design for Memristor-based Analog Neuromorphic Chip.
Proceedings of the 24th IEEE International Conference on High Performance Switching and Routing, 2023

2021
Predicting YOLO Misdetection by Learning Grid Cell Consensus.
Proceedings of the 20th IEEE International Conference on Machine Learning and Applications, 2021

2020
Exploiting uncertain timing information in time-based SAR ADCs.
IET Circuits Devices Syst., 2020

Accelerating low-voltage SAR ADC operation via comparator timing assisted and circuit adaptive tuning techniques.
IET Circuits Devices Syst., 2020

Digital LDO Based Power Signature Generation Circuit for IoT Security.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

MSB-First Distributed Arithmetic Circuit for Convolution Neural Network Computation.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Extracting Power Signature from Low Dropout Voltage Regulator for IoT Security.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2018
Digital LDO modelling techniques for performance estimation at early design stage.
IET Circuits Devices Syst., 2018

2017
Design Techniques for Direct Digital Synthesis Circuits with Improved Frequency Accuracy Over Wide Frequency Ranges.
J. Circuits Syst. Comput., 2017

2016
One-Step Sneak-Path Free Read Scheme for Resistive Crossbar Memory.
ACM J. Emerg. Technol. Comput. Syst., 2016

A comparator timing assisted SAR ADC technique with reduced conversion cycles.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Compressive image sensor technique with sparse measurement matrix.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Digital LDO modeling for early design space exploration.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A novel time and voltage based SAR ADC design with self-learning technique.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
A Low-Power Edge Detection Technique for Sensor Wake-Up Applications.
J. Circuits Syst. Comput., 2015

Design Techniques for Ultra-Low Voltage Comparator Circuits.
J. Circuits Syst. Comput., 2015

An A-SAR ADC circuit with adaptive auxiliary comparison scheme.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2014
An accelerated successive approximation technique for analog to digital converter design.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Adaptive compressive sensing for low power wireless sensors.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013
Enhancing Sensor Network Data Quality via Collaborated Circuit and Network Operations.
J. Sens. Actuator Networks, 2013

Addressing Memory Effect for rail-to-rail Comparator with Near-Threshold Supply voltage.
J. Circuits Syst. Comput., 2013

A novel envelope edge detector for ultra-low power sensor wake-up circuit.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
Short Pulse Generation With On-Chip Pulse-Forming Lines.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Reduction of Parasitic Capacitance Impact in Low-Power SAR ADC.
IEEE Trans. Instrum. Meas., 2012

2011
Hybrid pattern matching for trusted intrusion detection.
Secur. Commun. Networks, 2011

2010
Implementing self-testing and self-repairable analog circuits on field programmable analog array platforms.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A low power charge-redistribution ADC with reduced capacitor array.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Self-addressable memory-based FSM: a scalable intrusion detection engine.
IEEE Netw., 2009

Design of a window comparator with adaptive error threshold for online testing applications.
Microelectron. J., 2009

A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault Tolerance.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Implementing High-Speed String Matching Hardware for Network Intrusion Detection Systems.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2008

A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
A Programmable Window Comparator for Analog Online Testing.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Glitch Control with Dynamic Receiver Threshold Adjustment.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Fully Programmable Analog Window Comparator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.
J. Electron. Test., 2006

Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Minimizing FPGA Reconfiguration Data at Logic Level.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Design ofWindow Comparators for Integrator-Based Capacitor Array Testing Circuits.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005
A methodology to perform online self-testing for field-programmable analog array circuits.
IEEE Trans. Instrum. Meas., 2005

A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Minimum Cut Based Re-Synthesis Approach.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004
On-line Testing Field Programmable Analog Array Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002
Behavioral synthesis of field programmable analog array circuits.
ACM Trans. Design Autom. Electr. Syst., 2002


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