Hai Bing Yin
According to our database1,
Hai Bing Yin
authored at least 24 papers
between 2004 and 2018.
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Bibliography
2018
Three-level pipelined multi-resolution integer motion estimation engine with optimized reference data sharing search for AVS.
J. Real Time Image Process., 2018
Proceedings of the Advances in Multimedia Information Processing - PCM 2018, 2018
2017
Lossless image compression algorithm and hardware architecture for bandwidth reduction of external memory.
IET Image Process., 2017
2015
Fast Soft Decision Quantization With Adaptive Preselection and Dynamic Trellis Graph.
IEEE Trans. Circuits Syst. Video Technol., 2015
2014
A Regular VLSI Architecture of Motion Vector Prediction for Multiple-Standard MPEG-Like Video Codec.
J. Signal Process. Syst., 2014
An Efficient Lossless Image Compression Algorithm for External Memory Bandwidth Saving.
Proceedings of the Data Compression Conference, 2014
2013
Multiple target performance evaluation model for HD video encoder VLSI architecture design.
Proceedings of the 2013 Visual Communications and Image Processing, 2013
2011
Adaptive integer-precision Lagrange multiplier selection for high performance AVS video coding.
Proceedings of the 2011 IEEE Visual Communications and Image Processing, 2011
A highly efficient pipeline architecture of RDO-based mode decision design for AVS HD video encoder.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011
A hardware-efficient architecture for multi-resolution motion estimation using fully reconfigurable processing element array.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011
2010
IEEE Trans. Multim., 2010
A Hardware-Efficient Multi-Resolution Block Matching Algorithm and its VLSI Architecture for High Definition MPEG-Like Video Encoders.
IEEE Trans. Circuits Syst. Video Technol., 2010
Algorithm analysis and architecture design for rate distortion optimized mode decision in high definition AVS video encoder.
Signal Process. Image Commun., 2010
Digit. Signal Process., 2010
High throughput VLSI architecture for multiresolution integer motion estimation in high definition AVS video encoder.
Proceedings of the Visual Communications and Image Processing 2010, 2010
Proceedings of the Advances in Multimedia Information Processing - PCM 2010, 2010
Efficient macroblock pipeline structure in high definition AVS video encoder VLSI architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
VLSI friendly me search window buffer structure optimization and algorithm verification for high definition H.264/AVS video encoder.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
2008
An efficient VLSI architecture for rate disdortion optimization in AVS video encoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
An Improved Motion-Compensated 3-D LLMMSE Filter With Spatio-Temporal Adaptive Filtering Support.
IEEE Trans. Circuits Syst. Video Technol., 2007
An Improved Three-Step Hierarchical Motion Estimation Algorithm and Its Cost-Effective VLSI Architecture.
Proceedings of the Advances in Multimedia Information Processing, 2007
2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
2005
2004
A practical consistent-quality two-pass VBR video coding algorithm for digital storage application.
IEEE Trans. Consumer Electron., 2004